MIPI DPHY control register requires special handling since
it is shared between CSI (camera serial interface) and DSI
(display serial interface). By creating this clock
a serialized interface is provided for mipi-csi and mipi-dsi
drivers, so DPHYs may be safely controlled by both drivers.
Similarly dsim_dphy clock could be added for mipi-dsim.
---
I am not quite sure about "csis_dphy" clock, perhaps power domain
handling code would better place for MIPI DPHY control.
Signed-off-by: Sylwester Nawrocki <s.nawro...@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.p...@samsung.com>
---
arch/arm/mach-s5pv210/clock.c | 25 +++++++++++++++++++++++++
1 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 019c3a6..14e42ca 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -185,6 +185,19 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int
enable)
return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
}
+static int s5pv210_clk_mipi_dphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_MIPI_DPHY_CONTROL, clk, enable);
+}
+
+/* The common parent clock for mipi-csi/dsi clocks. */
+static struct clk clk_vp_mipi_dphy = {
+ .name = "vpclk_csis_dphy",
+ .id = -1,
+ .enable = s5pv210_clk_mipi_dphy_ctrl,
+ .ctrlbit = (1 << 0),
+};
+
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
.id = -1,
@@ -323,6 +336,18 @@ static struct clk init_clocks_disable[] = {
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4),
}, {
+ .name = "csis",
+ .id = -1,
+ .parent = &clk_pclk_dsys.clk,
+ .enable = s5pv210_clk_ip0_ctrl,
+ .ctrlbit = (1 << 31),
+ }, {
+ .name = "csis_dphy",
+ .id = -1,
+ .parent = &clk_vp_mipi_dphy,
+ .enable = s5pv210_clk_mipi_dphy_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
.name = "rot",
.id = -1,
.parent = &clk_hclk_dsys.clk,
--
1.7.1
--
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