Hi Kukjin and Arnd,

If there's chance to merge for 3.1 bugfix. It's required to run 2nd
GPIO banks for exynos4210.
and it should be applied for stable tree also.

Thank you,
Kyungmin Park

On Tue, Oct 18, 2011 at 7:16 PM, Marek Szyprowski
<m.szyprow...@samsung.com> wrote:
> Offsets of the irq controller registers were calculated correctly only
> for first GPIO bank. This patch fixes calculation of the register
> offsets for all GPIO banks.
>
> Reported-by: Sylwester Nawrocki <s.nawro...@samsung.com>
> Signed-off-by: Marek Szyprowski <m.szyprow...@samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.p...@samsung.com>
> ---
>  arch/arm/plat-s5p/irq-gpioint.c |    6 +++---
>  1 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
> index a566523..1fdfaa4 100644
> --- a/arch/arm/plat-s5p/irq-gpioint.c
> +++ b/arch/arm/plat-s5p/irq-gpioint.c
> @@ -163,9 +163,9 @@ static __init int s5p_gpioint_add(struct 
> samsung_gpio_chip *chip)
>        ct->chip.irq_mask = irq_gc_mask_set_bit;
>        ct->chip.irq_unmask = irq_gc_mask_clr_bit;
>        ct->chip.irq_set_type = s5p_gpioint_set_type,
> -       ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
> -       ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
> -       ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
> +       ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start);
> +       ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start);
> +       ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start);
>        irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
>                               IRQ_GC_INIT_MASK_CACHE,
>                               IRQ_NOREQUEST | IRQ_NOPROBE, 0);
> --
> 1.7.1.569.g6f426
>
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