On 26 February 2013 15:32, Russell King - ARM Linux <li...@arm.linux.org.uk> wrote: > On Tue, Feb 26, 2013 at 03:26:53PM +0530, Inderpal Singh wrote: >> Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence >> check >> the same before restoring the cache in resume. > > Why is this patch soo complicated? Can't you read the CPUs MIDR register > from assembly code?
I wanted to read MIDR only once thats why didn't read in resume function in assembly as the same resume function gets used in cpuidle path. Regards, Inder -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
