On Mon, Jun 16, 2014 at 4:56 PM, Tushar Behera <trbli...@gmail.com> wrote: > On 06/11/2014 09:28 PM, Javier Martinez Canillas wrote: >> On Wed, Jun 11, 2014 at 7:32 AM, Tushar Behera <tusha...@samsung.com> wrote: >>> Currently CLK_FOUT_EPLL was set as one of the parents of AUDSS mux. >>> As per the user manual, it should be CLK_MAU_EPLL. >>> >>> The problem surfaced when the bootloader in Peach-pit board set >>> the EPLL clock as the parent of AUDSS mux. While booting the kernel, >>> we used to get a system hang during late boot if CLK_MAU_EPLL was >>> disabled. >>> >>> Signed-off-by: Tushar Behera <tusha...@samsung.com> >>> Signed-off-by: Shaik Ameer Basha <shaik.am...@samsung.com> >>> Reported-by: Kevin Hilman <khil...@linaro.org> >>> --- >>> arch/arm/boot/dts/exynos5420.dtsi | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi >>> b/arch/arm/boot/dts/exynos5420.dtsi >>> index e385322..79e9119 100644 >>> --- a/arch/arm/boot/dts/exynos5420.dtsi >>> +++ b/arch/arm/boot/dts/exynos5420.dtsi >>> @@ -167,7 +167,7 @@ >>> compatible = "samsung,exynos5420-audss-clock"; >>> reg = <0x03810000 0x0C>; >>> #clock-cells = <1>; >>> - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, >>> + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, >>> <&clock CLK_SCLK_MAUDIO0>, <&clock >>> CLK_SCLK_MAUPCM0>; >>> clock-names = "pll_ref", "pll_in", "sclk_audio", >>> "sclk_pcm_in"; >>> }; >>> -- >>> 1.7.9.5 >>> >>> -- >> >> Tested-by: Javier Martinez Canillas <javier.marti...@collabora.co.uk> >> > > Kukjin, > > Would you please take this patch as a fix for 3.16? > > -- > Tushar Behera
Kukjin, Please pick this patch for 3.16. This is an essential fix required for Peach-pit/Peach-pi board. -- Tushar Behera -- To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
