> Hi , > > I need some suggestion . > > From the below interrupt handler in libahci.c it explains that the > interrupt from port to Host is level triggered. Do we have any > existing implementation that handles the port to Host as Edge > triggered.
Not that I know of but if it works as a edge triggered latch, would it need anything done different? We met a scenario which explains the below : 1. PxIS0 raised set to 1 and Host IS detects a level . After some interval PxIS1 raised and Host IS detects a level and interrupt service routine clear and it work. This is as per the libahci implementation 2. PxIS0 set to 1 and Host IS detects a edge . After some interval PxIS1 raised and Host IS detects a edge but ISR implementation is level trigger so it looses interrupts. Was asking about this scenario ?? On Fri, Apr 17, 2015 at 8:12 PM, Tejun Heo <t...@kernel.org> wrote: > On Fri, Apr 17, 2015 at 04:22:17PM +0530, Suman Tripathi wrote: >> Hi , >> >> I need some suggestion . >> >> From the below interrupt handler in libahci.c it explains that the >> interrupt from port to Host is level triggered. Do we have any >> existing implementation that handles the port to Host as Edge >> triggered. > > Not that I know of but if it works as a edge triggered latch, would it > need anything done different? > > -- > tejun -- Thanks, with regards, Suman Tripathi -- To unsubscribe from this list: send the line "unsubscribe linux-scsi" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
