On Sun, 4 Oct 1998, Adam D. McKenna wrote:
> I was under the impression that the PPro was considered superior architecture
> to the PII, even though it's older.
The one thing that made the PPro "superior" to the PII was that -- until
recently -- the cache on the PPro ran at the full speed of the clock
while the cache on the PII ran at half clock speed. The new Xeon family
of PII's as well as the A series Celerons now run the cache at full
clock speed.
The speed of the cache is only one of many factors in CPU performance,
however. Raw CPU clock for a given processor generation is, to my
direct experience borne of many, many measurements, by far the primary
determinant. Raw clock determines the "baseline" performance and things
like cache size, cache speed, memory speed all modify this baseline and
can give a small edge or create a small penalty (where "small" is, for
most code, roughly a factor of 10%).
The PPro and PII are actually remarkably similar as far as the non-cache
design is concerned, and if anything the PII has a small edge there at
constant clock. The (non-Xeon, non-Celeron) PII loses a bit in RELATIVE
cache speed, but at 300 MHz half speed is still 150 MHz, almost as fast
as your PPro's. The PII gains tremendously in cache size. 512 caches
will run many code mixes 10% faster than 256K caches even on otherwise
identical CPUs (again, my own measurements of numerical jobs of various
sizes). Intel certain values it -- for a while they charged nearly
twice as much for a 512K cache PPro as they did for a 256K cache PPro at
the same clock. PII systems support SDRAM. Even at the relatively slow
LX pace of 66 MHz memory clock (same as the PPro) SDRAM makes a big
difference (although by now PPro motherboards may exist that can handle
SDRAM). Finally, a 440BX PII system can run SDRAM at 100 MHz and 7 ns.
To bring the Celeron (at one point, a slightly crippled PII) back into
the discussion -- when the Celeron had no cache, it was a miserable
excuse for a CPU IMHO. However, as was pointed out to me on this list
a week or two ago in the new A series it now sports not only a 128K
cache, but one running at full clock speed. For many code mixes the
humble Celeron will beat its larger-but-slower-cache cousin the full PII
at equivalent clock -- by a hair (~10%) of course. For others it will
still lose by ~10%. Big jobs probably favor a real PII, multitasking
and jobs without too big a memory stride will favor the Celeron. I'm
getting a 300A system tomorrow and can run some direct comparisons with
my existing 300 MHz dual PII on single-threaded code. If you are
interested, I'll post back the results.
Anyway, all this is theory (and a summary of personal experience). The
actual experiences are that when I run my Monte Carlo code on one of my
many 200 MHz PPro systems and my many 300 MHz or 400 MHz PII systems, it
completes a bit better than twice as fast on the 400 MHz systems (with
their 100 MHz memory buses and caches running as fast as those on the
PPro's anyway and twice the cache) and just about exactly 1.5 times as
fast on the 300 MHz systems. Interpretation: there is a clear tend
toward overall improvement as the PPro->PII->? family evolves to higher
clock. For early PII's, they compromised the cache clock to increase
the prime performance determinant (the CPU clock) but made enough other
improvements to pretty much compensate. For recent PII's overall
systems improvements have more than compensated for the halved cache
clock. For current PII's (exemplified by the Xeon and Celeron at the
high and low ends) they have kept all the improvements and added a full
speed cache. The PII is clearly superior to the PPro, the PPro is
doomed and being sold as cheaply as it is because it is end-of-life
technology, and I personally would rather have a single 300 MHz Celeron
than any two PPros for anything except maybe service as a beowulf node
(where I could at least hope to keep both PPros churning 90% of the time
on big code where their cache size and speed advantage makes SOME
difference).
As always, the analysis above represents the best of my knowledge at
this moment. Experts on the list should feel free to correct it --
history has shown (re: the recent 300A Celeron discussion:-) that it may
well contain mistakes.
rgb
Robert G. Brown http://www.phy.duke.edu/~rgb/
Duke University Dept. of Physics, Box 90305
Durham, N.C. 27708-0305
Phone: 1-919-660-2567 Fax: 919-660-2525 email:[EMAIL PROTECTED]
