I'm putting this on the smp thread as possible linus get so much mail at lins@.....
Hi - This is go # 2 on this message cuz try #1 accidently was sent before I finished typing it.... My dad (Tom Watson, [EMAIL PROTECTED]) forwarded me your origional question. Here at Ascend, I am working with the PII and Intel 440BX chipset. I did a little looking with our OS guy and we came up with some info about the ELCR in the 82371AB PCI-TO-ISA/IDE Xcelerator (PIIX4) manuals on p.79 & p. 175. You can grab it from this address at Intel's web site: http://www.intel.com/design/pcisets/datashts/290562.htm The manual indicates that the ELCR (on the PIIX4) expects an active high on the coresponding IRQ input. I don't know if this applies to all Intel chipsets, but it seems reasonable that it does. In the reading I did of this material, they explicitly state the level is acitive high several times as the expected mode. The manual also talks about the timing of the signals and what order they have to happen (i.e. the IRQ input must remain high until after the falling edge of INTA#, etc...) If other chipset makers use an active low you may be stuck....Hope this helps.... Jon Watson [EMAIL PROTECTED] ******************************************* Core Software Engineering Ascend Communications, Westford, MA 978-952-1670 ******************************************* >To: [EMAIL PROTECTED] >From: [EMAIL PROTECTED] (Linus Torvalds) >Subject: Anybody with IRQ insights? >Date: 29 Sep 1998 19:22:06 GMT >Organization: Transmeta Corporation, Santa Clara, CA >Message-ID: <6urc0u$qos$[EMAIL PROTECTED]> >X-Orcpt: rfc822;[EMAIL PROTECTED] >Sender: [EMAIL PROTECTED] >Precedence: bulk >X-Loop: [EMAIL PROTECTED] > > >As of Linux-2.1.123, intel Linux/SMP will query the so-called ELCR >("Edge/Level Control Register") to find out whether a legacy IRQ is >supposed to be edge-triggered or level-triggered. > >The problem for me is that I seem to have no clue about the polarity of >the interrupt. The (scant) documentation I have seems to imply that >level-triggered interrupts are always active low, and that the polarity >should thus be "1" in the IO-APIC. And that works apparently correctly >on the machines I had access to (admittedly few of them actually use >many legacy interrupts - one of the joys of having recent hardware). > >However, I also have a report of one machine where it appears that the >level-trigger interrupts are active high. And my changes result in >endless interrupts on such a machine. Understandable, but incorrect ;) > >I can make it a bootup option, but it would be even better if somebody >out there has a clue, and can tell me that "duh, Linus, you're just >being dense, look at line XXXX in manual YYYY and they tell you that >..." > >Any clues? I may end up having to disable the new code unless something >better comes along.. > > Linus >
