The very first Tyan Tomcat II's had the exact same problem. Using 2 CPU's ,
as I understand it, literally pummels the cache on a P5 system under a heavy
load. It took Tyan about three revs to get it right. I used to work for a
VAR that had an agreement with Tyan that basically amounted to us receiving
the boards early so that we would have them on release date for sale. We
sent all of the first two revisions of the Tomcat II's back and the COAST
modules that came with the third rev. The reason I mentioned is the same
that was given to me by Tyan tech support over 2 years ago.
I didn't check but does this board use a COAST module? Ultimately Tyan
claimed the early COAST spec insufficient for SMP system and began to solder
the cache on to their dual baords.
Hope this helps.
-----------------------------------------------------------
Jeremy Smith
System Administrator
Bell+Howell MPS
[EMAIL PROTECTED] <mailto:[EMAIL PROTECTED]>
[EMAIL PROTECTED] <mailto:[EMAIL PROTECTED]>
Day: (919)767-6530
Eve: (919)859-5690
"Truth in philosophy means that concept and external reality correspond."
George Hegel (1770-1831)
------------------------------------------------------------
-----Original Message-----
From: Norbert Lesch
[mailto:[EMAIL PROTECTED]]
Sent: Monday, October 19, 1998 11:37 AM
To: [EMAIL PROTECTED];
[EMAIL PROTECTED]
Subject: Asus P55 T2D4P, Problems with Cache using
smp-linux
Hello SMP-users,
I use the Asus P55T2P4D (dual Pentium PCI/EISA) mainboard,
128MByte EDO
Memory (4*32MByte), 512kByte 2.level Cache Module Asus CM1
Rev. 1.6,
2 Intel Pentium233MMX Processors, stepping 3, kernel
2.0.35, symbios
20810 SCSI controller
The Problem :
In single CPU mode the board is stable (that means 200
kernel compiles
using make -j without an error), no matter which CPU of
the two is
used! If both cpus are plugged in, the board is stable too
if I use the
non SMP kernel, if I use the SMP enabled kernel and switch
of Dual CPU
support by jumper on the motherboard the board remains
stable.
I conclude: RAM, CPUs, and Cache ok!
If I use the SMP-kernel with dual cpu support enabled on the
motherboard
the 2 CPUs are recognized (each 460 bogomips) but the board
gets
unstable, 1 of 5 kernel compiles gets signal 11. The system
gets stable
again if I switch off the 2. level Cache, if I reduce Cache
size by
jumper to 256k I get approximately 1 out of 10 faulty kernel
compiles.
This happens with Bios revision td5e0107 and 0106.
I think the Cache module is broken, but why does it work in
single CPU
mode, maybe there is something wrong on the board itself?
Who has
experience with this board? Which Cache module can I use
instead?
Thanks
Norbert
