>From: Tigran Aivazian <[EMAIL PROTECTED]> >I am aware of MP spec saying on page 4-10 > > "each bus is assigned a unique bus ID number by BIOS" > >and then on page 4-11 > > "If the bus looks like a part of another bus because it uses a > subset of that bus's interrupts and address space, rendering it > totally invisible to software, it does not need its own bus entry > in the table. The two buses are then considered a single logical > bus." > >Is the above enough justification? Couldn't BIOS manufacturer argue that >since the brigde does the job of mapping the address space etc by the >PCI-PCI bridge spec then the bus behind the bridge does indeed become >"totally invisible to software" in accordance with MP spec? >Maybe not... any ideas? > A PCI-PCI bridge doesn't map PCI configuration space of the PCI bus behind the bridge so this bus has to have its own entry in the MP table. For example, the OS detected a PCI device on bus 3, device 5, function 0, so the OS _has_ to know the connection of the interrupt line of this device to the IO APIC pin. Thus, MPT interrupt entry for this device has to have bus 3 as the source of the interrupt. OK, that is bus 3? Is it PCI, ISA or NuBus? Thus the MP table has to have the entry for this bus. Dmitriy Budko [EMAIL PROTECTED] BeOS kernel developer
