> Where (and how) do we decide to (re)map the PCI (device,pin) pairs to
> IRQs when we are using the APIC? In particular, what is happening is
> that I have two PCI cards which both use INTA, and seem to be in slots
> (1 and 5) where these two INTA pins are connected to the same PIRQ
For full details, see the MP spec at:
ftp://download.intel.com/design/pro/datashts/24201606.pdf
The basics are:
1) In PIC mode, the PCI slots IRQs must be braided and have INTA-D routed to
ISA IRQs.
2) How a board behaves in APIC mode is up to the manufacturer. A really cheap
implementation may retain the braiding and route the PCI irqs straight onto
ISA IRQs via the APIC (the Acer Altos 9000 does this). A rolls-royce
implementation would disable the braiding in APIC mode and route each card's
INTA-D to a separate IO-APIC pin (the intel ALDER nearly does this. In
practice the 4 IRQs per slot is so wasteful that good SMP boards use an
intelligent router between the slots and the IO-APIC pins).
3) If your IO-APIC has >16 pins, you get more than 16 IRQs (the latest
IO-APICs in the 4 way Xeons have 64 pins).
4) Because the complexity is so high, the board must tell the O/S what will
happend in APIC mode. It does this via the MP-BIOS. The pirq kernel option
provides a way to override the MP-BIOS in the event it is wrong, but
realistically if the board manufacturer can't get the MP-BIOS right I wouldn't
hold out too much hope that they got the IO-APIC routing circuitry right
either.
One of the reasons why your board could be hanging is an Edge/Level interrupt
problem instead.
James Bottomley
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