> If I compare differences between those files, that are supposed
> to be the same, I obtain :
> 5649c5649
> < 00169b0 4697 9c90 6e6a ccbf 77ea bd59 cc2b 6186
> ---
> > 00169b0 4697 9c90 ee6a ccbf 77ea bd59 cc2b 6186
6e->ee is 1 bit (01101110 -> 11101110)
> 21770c21770
> < 0055940 5a9d ad36 37a4 bb45 3144 c56c 4c70 e7a4
4c->cc is 1 bit (01001100 -> 11001100)
> > 0055940 5a9d ad36 37a4 bb45 3144 c56c cc70 e7a4
> WARNING: SMP operation may be unreliable with B stepping processors.
> enabling symmetric IO mode... ...done.
B step Pentiums. Thats ominous anyway.
> I guess that B stepping processors could be the cause of the problem.
> I read the doc in ./arch/i386/kernel/smp.c but this is not very clear
> to me. Does a workaround exist for this case ? Thanks for your help.
The B step pentiums bugs wouldnt explain this. You'd expect to lose IRQs,
or see the machine freeze. One of those CPU's is very old though.
With the Pentium the rules for pairing chips are very explicit. The early
B series chips also have problems with REP MOVS on 100Mhz parts and the like.
The errata document makes interesting reading.
I don't believe B1 and B6 is a legal pairing of CPU's. Intel should be able
to tell you if it is. The rules for Pentiums especially old ares quite limiting
compared to the current CPUs.
Alan
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