> > cycles_t cacheflush_time = 1000000; /* 1M cache on SS/50 at 50MB/s */
> > improves performance noticably. the point is that in the XXX version,
> > processes will be prone to migrate across CPUs at the drop of a hat...
>
> You might want to look at arch/i386/kernel/smpboot.c
>
> There's a reasonably simple calculation there that sets
> the value of cacheflush_time based on some (measured)
> constants.
that's because I wrote it! ;)
> If SPARC gives you the information x86 gives you, you
it doesn't, or at least the kernel doesn't current obtain it.
the sparc64 port actually tries to measure dram bandwidth,
which is a very good thing (something I'd like to see in ia32
and other ports). it's fairly easy to determine cache size
for all ia32 CPUs; I have no idea whether it's easy on other ports.
regards, mark hahn.
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