On 1/15/21 11:28 AM, Shahab Vahedi wrote: >>> + cpu_stl_data(env, tmp_sp, CPU_FP(env)); >>> + } >> >> And what if these stores raise an exception? I doubt you're going to get an >> exception at the correct pc. > > I've added a few bad-weather test cases [1] and they work as expected. Indeed, > none of those tests trigger an exception during the "cpu_stl_data()". Could > you > elaborate why you think the PC might be incorrect? Then I can add the > corresponding > tests and fix the behavior.
Because you're using cpu_stl_data_ra, with GETPC, if the store faults (e.g. SIGSEGV) then the exception unwind will not be done. This will happen to work ok if and only if "enter" is the first insn of the TB. >> In the case of enter or leave, this is one load/store plus one addition, >> followed by a branch. All of which is encoded as fields in the instruction. >> Extremely simple. > > You're suggesting that "enter/leave" should use TCG opcodes instead of > helpers? If yes, do you really think it is possible to implement each with ~10 > opcodes? More or less. Two per registers stored, plus two moves. It looks like the limit of registers is either 3 or 14, depending on the cpu configuration. Certainly this is no different from other "push multiple" type of instructions of other architectures, which do exactly this. r~ _______________________________________________ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-snps-arc
