On Sat, Jan 11, 2014 at 4:19 PM, Carlo Caione <carlo.cai...@gmail.com> wrote: > Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI. > Three register are present to (un)mask, control and acknowledge NMI. > These two patches add a new irqchip driver in cascade with GIC. > > Changes since v1: > - added binding document > > Changes since v2: > - fixed trigger type in DTS > - new explanations in binding documentation > - added support for A31 (sun6i)
Ping -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/groups/opt_out.
