Signed-off-by: Ian Campbell <i...@hellion.org.uk>
---
arch/arm/cpu/armv7/sunxi/clock.c | 10 ++++++----
arch/arm/include/asm/arch-sunxi/clock.h | 9 +++++++++
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index 54d801c..980fb90 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -26,7 +26,7 @@ static void clock_init_safe(void)
APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
- writel(0xa1005000, &ccm->pll1_cfg);
+ writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
sdelay(200);
writel(AXI_DIV_1 << AXI_DIV_SHIFT |
AHB_DIV_2 << AHB_DIV_SHIFT |
@@ -36,11 +36,13 @@ static void clock_init_safe(void)
#ifdef CONFIG_SUN5I
/* Power on reset default for PLL6 is 2400 MHz, which is faster then
* it can reliable do :| Set it to a 600 MHz instead. */
- writel(0x21009911, &ccm->pll6_cfg);
+ writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
#endif
#ifdef CONFIG_SUN7I
- writel(0x1 << 6 | readl(&ccm->ahb_gate0), &ccm->ahb_gate0);
- writel(0x1 << 31 | readl(&ccm->pll6_cfg), &ccm->pll6_cfg);
+ writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
+ &ccm->ahb_gate0);
+ writel(0x1 << PLL6_ENABLE_OFFSET | readl(&ccm->pll6_cfg),
+ &ccm->pll6_cfg);
#endif
}
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 533f9b5..dc8c371 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -117,6 +117,15 @@ struct sunxi_ccm_reg {
#define CPU_CLK_SRC_OSC24M 1
#define CPU_CLK_SRC_PLL1 2
+#define PLL1_CFG_DEFAULT 0xa1005000
+
+#ifdef CONFIG_SUN5I
+#define PLL6_CFG_DEFAULT 0x21009911
+#endif
+#ifdef CONFIG_SUN7I
+#define PLL6_ENABLE_OFFSET 31
+#endif
+
#ifdef CONFIG_SUN5I
#define AHB_CLK_SRC_AXI 0
#endif
--
1.8.5.3
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