Hi,
On 03/17/2014 09:39 AM, Chen-Yu Tsai wrote:
> On Mon, Mar 17, 2014 at 4:28 PM, Ian Campbell <i...@hellion.org.uk> wrote:
>> On Mon, 2014-03-17 at 12:05 +0800, Chen-Yu Tsai wrote:
>>> @@ -162,40 +151,47 @@ static int mmc_clk_io_on(int sdc_no)
>>> switch (sdc_no) {
>>> case 0:
>>> /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
>>> - writel(0x222222, &gpio_f->cfg[0]);
>>> - writel(0x555, &gpio_f->pull[0]);
>>> - writel(0xaaa, &gpio_f->drv[0]);
>>> + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
>>> + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0_CMD);
>>
>> I appreciate that the function is the same for each pin but this still
>> looks odd. Perhaps just #define SUNXI_GPFx_SDC0 and use that?
>
> I was matching what was already defined, but yeah, that looks better.
> Maybe we should change the other existing one as well?
> I'm referring to the whole patch series, and the ones already in gpio.h.
Can you respin this one with this fixed then? Then I'll add the
whole series to u-boot-sunxi sunxi branch.
Thanks & Regards,
Hans
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