With this patch and built with SPL,NO_AXP options added, it is possible
to build a non-functional SPL for the A31, which will properly load and
print its banner on the serial console:
U-Boot SPL 2014.04-rc2-01254-g7e81174-dirty (Mar 28 2014 - 21:09:16)
Board: Colombus
sun6i SPL support is not yet complete
Signed-off-by: Hans de Goede <hdego...@redhat.com>
---
arch/arm/cpu/armv7/sunxi/Makefile | 4 +++-
arch/arm/cpu/armv7/sunxi/board.c | 5 +++++
arch/arm/cpu/armv7/sunxi/clock.c | 19 ++++++++++++++++++-
arch/arm/include/asm/arch-sunxi/clock-sun6i.h | 18 ++++++++++++++++++
board/sunxi/board.c | 5 ++---
include/configs/sunxi-common.h | 2 ++
6 files changed, 48 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 3b8da3e..e9737a3 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -30,7 +30,9 @@ endif
endif
ifdef CONFIG_SPL_BUILD
-obj-y += dram.o
+obj-$(CONFIG_SUN4I) += dram.o
+obj-$(CONFIG_SUN5I) += dram.o
+obj-$(CONFIG_SUN7I) += dram.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 0d954da..f01d38b 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -112,8 +112,13 @@ void s_init(void)
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
+#ifdef CONFIG_SUN6I
+ printf("sun6i SPL support is not yet complete\n");
+ hang();
+#else
sunxi_board_init();
#endif
+#endif
}
#ifndef CONFIG_SYS_DCACHE_OFF
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
index a178eea..05b8d27 100644
--- a/arch/arm/cpu/armv7/sunxi/clock.c
+++ b/arch/arm/cpu/armv7/sunxi/clock.c
@@ -21,6 +21,19 @@ static void clock_init_safe(void)
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
/* Set safe defaults until PMU is configured */
+#if defined(CONFIG_SUN6I)
+ /* AXI and PLL1 settings from boot0 / boot1, PLL1 set to 486 Mhz */
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+ writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg);
+ sdelay(200);
+ writel(AXI_DIV_3 << AXI_DIV_SHIFT |
+ ATB_DIV_2 << ATB_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
+ &ccm->cpu_axi_cfg);
+#else
writel(AXI_DIV_1 << AXI_DIV_SHIFT |
AHB_DIV_2 << AHB_DIV_SHIFT |
APB0_DIV_1 << APB0_DIV_SHIFT |
@@ -33,6 +46,7 @@ static void clock_init_safe(void)
APB0_DIV_1 << APB0_DIV_SHIFT |
CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
&ccm->cpu_ahb_apb0_cfg);
+#endif
#ifdef CONFIG_SUN7I
writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0),
&ccm->ahb_gate0);
@@ -59,6 +73,9 @@ int clock_init(void)
/* open the clock for uart */
sr32(&ccm->apb2_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
+ /* deassert uart reset */
+ sr32((u32 *)SUN6I_ABP2_RESET_BASE, 16 + CONFIG_CONS_INDEX - 1, 1, 1);
+
/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
#else
@@ -126,7 +143,7 @@ int clock_twi_onoff(int port, int state)
return 0;
}
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SUN6I)
#define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \
16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
(K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)
diff --git a/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
index 2f20d5d..1d15c4d 100644
--- a/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock-sun6i.h
@@ -141,6 +141,23 @@ struct sunxi_ccm_reg {
#define APB2_FACTOR_M 0
#define APB2_FACTOR_N 0
+/* cpu_axi_cfg bits */
+#define AXI_DIV_SHIFT 0
+#define ATB_DIV_SHIFT 8
+#define CPU_CLK_SRC_SHIFT 16
+
+#define AXI_DIV_1 0
+#define AXI_DIV_2 1
+#define AXI_DIV_3 2
+#define AXI_DIV_4 3
+#define ATB_DIV_1 0
+#define ATB_DIV_2 1
+#define ATB_DIV_4 2
+#define CPU_CLK_SRC_OSC24M 1
+#define CPU_CLK_SRC_PLL1 2
+
+#define PLL1_CFG_DEFAULT 0x90011b21
+
#define PLL6_CFG_DEFAULT 0x90041911
#define AHB_GATE_OFFSET_MMC3 11
@@ -155,6 +172,7 @@ struct sunxi_ccm_reg {
#define CCM_MMC_CTRL_ENABLE (0x1 << 31)
#define SUN6I_ABP1_RESET_BASE 0x01c202c0
+#define SUN6I_ABP2_RESET_BASE 0x01c202d8
#define ABP1_RESET_OFFSET_MMC3 11
#define ABP1_RESET_OFFSET_MMC2 10
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 873eb2a..ddc66cc 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -74,7 +74,7 @@ int board_mmc_init(bd_t *bis)
}
#endif
-#ifdef CONFIG_SPL_BUILD
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SUN6I)
void sunxi_board_init(void)
{
int power_failed = 0;
@@ -119,6 +119,7 @@ void sunxi_board_init(void)
else
printf("Failed to set core voltage! Can't set CPU frequency\n");
}
+#endif
#if defined(CONFIG_SPL_OS_BOOT) && defined(CONFIG_AXP209_POWER)
int spl_start_uboot(void)
@@ -137,5 +138,3 @@ void spl_display_print(void)
printf("Board: %s\n", CONFIG_SYS_BOARD_NAME);
}
#endif
-
-#endif
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 212b621..4a562ac 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -326,7 +326,9 @@
#undef CONFIG_CMD_NFS
/* I2C */
+#ifndef CONFIG_SUN6I
#define CONFIG_SPL_I2C_SUPPORT
+#endif
#define CONFIG_SYS_I2C_SPEED 400000
#define CONFIG_HARD_I2C
#define CONFIG_SUNXI_I2C
--
1.9.0
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