Hi,
On 04/18/2014 11:45 AM, Ian Campbell wrote:
> "sunxi: remove magic numbers from clock_get_pll{5,6}" left the clock_get_pll5
> prototpye after removing the function itself.
>
> also the prevailing style in clock_sun?i.h is for spaces around "<<", so
> update
> the new #defines to match.
>
> Signed-off-by: Ian Campbell <[email protected]>
> Cc: Chen-Yu Tsai <[email protected]>
Thanks, applied and pushed.
Regards,
Hans
> ---
> arch/arm/include/asm/arch-sunxi/clock.h | 1 -
> arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 30
> +++++++++++++--------------
> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 30
> +++++++++++++--------------
> 3 files changed, 30 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
> b/arch/arm/include/asm/arch-sunxi/clock.h
> index a034e0b..2f580b7 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> @@ -25,7 +25,6 @@
> int clock_init(void);
> int clock_twi_onoff(int port, int state);
> void clock_set_pll1(int hz);
> -unsigned int clock_get_pll5(void);
> unsigned int clock_get_pll6(void);
> void clock_init_safe(void);
> void clock_init_uart(void);
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> index 1d4b265..0eea108 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
> @@ -91,23 +91,23 @@ struct sunxi_ccm_reg {
> };
>
> /* apb1 bit field */
> -#define APB1_CLK_SRC_OSC24M (0x0<<24)
> -#define APB1_CLK_SRC_PLL6 (0x1<<24)
> -#define APB1_CLK_SRC_LOSC (0x2<<24)
> -#define APB1_CLK_SRC_MASK (0x3<<24)
> -#define APB1_CLK_RATE_N_1 (0x0<<16)
> -#define APB1_CLK_RATE_N_2 (0x1<<16)
> -#define APB1_CLK_RATE_N_4 (0x2<<16)
> -#define APB1_CLK_RATE_N_8 (0x3<<16)
> -#define APB1_CLK_RATE_N_MASK (3<<16)
> -#define APB1_CLK_RATE_M(m) (((m)-1)<<0)
> -#define APB1_CLK_RATE_M_MASK (0x1f<<0)
> +#define APB1_CLK_SRC_OSC24M (0x0 << 24)
> +#define APB1_CLK_SRC_PLL6 (0x1 << 24)
> +#define APB1_CLK_SRC_LOSC (0x2 << 24)
> +#define APB1_CLK_SRC_MASK (0x3 << 24)
> +#define APB1_CLK_RATE_N_1 (0x0 << 16)
> +#define APB1_CLK_RATE_N_2 (0x1 << 16)
> +#define APB1_CLK_RATE_N_4 (0x2 << 16)
> +#define APB1_CLK_RATE_N_8 (0x3 << 16)
> +#define APB1_CLK_RATE_N_MASK (3 << 16)
> +#define APB1_CLK_RATE_M(m) (((m)-1) << 0)
> +#define APB1_CLK_RATE_M_MASK (0x1f << 0)
>
> /* apb1 gate field */
> #define APB1_GATE_UART_SHIFT (16)
> -#define APB1_GATE_UART_MASK (0xff<<APB1_GATE_UART_SHIFT)
> +#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT)
> #define APB1_GATE_TWI_SHIFT (0)
> -#define APB1_GATE_TWI_MASK (0xf<<APB1_GATE_TWI_SHIFT)
> +#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT)
>
> /* clock divide */
> #define AXI_DIV_SHIFT (0)
> @@ -223,9 +223,9 @@ struct sunxi_ccm_reg {
> #define CCM_PLL5_CTRL_EN (0x1 << 31)
>
> #define CCM_PLL6_CTRL_N_SHIFT 8
> -#define CCM_PLL6_CTRL_N_MASK (0x1f<<CCM_PLL6_CTRL_N_SHIFT)
> +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
> #define CCM_PLL6_CTRL_K_SHIFT 4
> -#define CCM_PLL6_CTRL_K_MASK (0x3<<CCM_PLL6_CTRL_K_SHIFT)
> +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
>
> #define CCM_GPS_CTRL_RESET (0x1 << 0)
> #define CCM_GPS_CTRL_GATE (0x1 << 1)
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 382f296..c524c29 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -137,23 +137,23 @@ struct sunxi_ccm_reg {
> };
>
> /* apb2 bit field */
> -#define APB2_CLK_SRC_LOSC (0x0<<24)
> -#define APB2_CLK_SRC_OSC24M (0x1<<24)
> -#define APB2_CLK_SRC_PLL6 (0x2<<24)
> -#define APB2_CLK_SRC_MASK (0x3<<24)
> -#define APB2_CLK_RATE_N_1 (0x0<<16)
> -#define APB2_CLK_RATE_N_2 (0x1<<16)
> -#define APB2_CLK_RATE_N_4 (0x2<<16)
> -#define APB2_CLK_RATE_N_8 (0x3<<16)
> -#define APB2_CLK_RATE_N_MASK (3<<16)
> -#define APB2_CLK_RATE_M(m) (((m)-1)<<0)
> -#define APB2_CLK_RATE_M_MASK (0x1f<<0)
> +#define APB2_CLK_SRC_LOSC (0x0 << 24)
> +#define APB2_CLK_SRC_OSC24M (0x1 << 24)
> +#define APB2_CLK_SRC_PLL6 (0x2 << 24)
> +#define APB2_CLK_SRC_MASK (0x3 << 24)
> +#define APB2_CLK_RATE_N_1 (0x0 << 16)
> +#define APB2_CLK_RATE_N_2 (0x1 << 16)
> +#define APB2_CLK_RATE_N_4 (0x2 << 16)
> +#define APB2_CLK_RATE_N_8 (0x3 << 16)
> +#define APB2_CLK_RATE_N_MASK (3 << 16)
> +#define APB2_CLK_RATE_M(m) (((m)-1) << 0)
> +#define APB2_CLK_RATE_M_MASK (0x1f << 0)
>
> /* apb2 gate field */
> #define APB2_GATE_UART_SHIFT (16)
> -#define APB2_GATE_UART_MASK (0xff<<APB2_GATE_UART_SHIFT)
> +#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT)
> #define APB2_GATE_TWI_SHIFT (0)
> -#define APB2_GATE_TWI_MASK (0xf<<APB2_GATE_TWI_SHIFT)
> +#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT)
>
> /* cpu_axi_cfg bits */
> #define AXI_DIV_SHIFT 0
> @@ -175,9 +175,9 @@ struct sunxi_ccm_reg {
> #define PLL6_CFG_DEFAULT 0x90041911
>
> #define CCM_PLL6_CTRL_N_SHIFT 8
> -#define CCM_PLL6_CTRL_N_MASK (0x1f<<CCM_PLL6_CTRL_N_SHIFT)
> +#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
> #define CCM_PLL6_CTRL_K_SHIFT 4
> -#define CCM_PLL6_CTRL_K_MASK (0x3<<CCM_PLL6_CTRL_K_SHIFT)
> +#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
>
> #define AHB_GATE_OFFSET_MMC3 11
> #define AHB_GATE_OFFSET_MMC2 10
>
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