On Sun, Apr 27, 2014 at 2:19 AM, Hans de Goede <hdego...@redhat.com> wrote: > Hi, > > On 04/24/2014 06:39 PM, Chen-Yu Tsai wrote: >> Also rewrite sunxi_mmc clock gate/reset enabling code using >> setbits_le32. >> >> Signed-off-by: Chen-Yu Tsai <w...@csie.org> > > This causes an unused variable rval warning, I've fixed this in my > local tree.
Looks good. Thanks ChenYu >> --- >> arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 4 ++-- >> arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 17 ++++++++++------- >> drivers/mmc/sunxi_mmc.c | 8 ++------ >> 3 files changed, 14 insertions(+), 15 deletions(-) >> >> diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c >> b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c >> index 1f1f11c..c27d1ff 100644 >> --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c >> +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c >> @@ -68,8 +68,8 @@ void clock_init_uart(void) >> CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT+CONFIG_CONS_INDEX-1)); >> >> /* deassert uart reset */ >> - setbits_le32((u32 *)SUN6I_ABP2_RESET_BASE, >> - 1 << (16 + CONFIG_CONS_INDEX - 1)); >> + setbits_le32(&ccm->apb2_reset_cfg, >> + 1 << (APB2_RESET_UART_SHIFT+CONFIG_CONS_INDEX-1)); >> >> /* Dup with clock_init_safe(), drop once sun6i SPL support lands */ >> writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); >> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h >> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h >> index 1861673..88b1d1f 100644 >> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h >> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h >> @@ -190,13 +190,16 @@ struct sunxi_ccm_reg { >> >> #define CCM_MMC_CTRL_ENABLE (0x1 << 31) >> >> -#define SUN6I_ABP1_RESET_BASE 0x01c202c0 >> -#define SUN6I_ABP2_RESET_BASE 0x01c202d8 >> +#define AHB_RESET_OFFSET_MMC3 11 >> +#define AHB_RESET_OFFSET_MMC2 10 >> +#define AHB_RESET_OFFSET_MMC1 9 >> +#define AHB_RESET_OFFSET_MMC0 8 >> +#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) >> >> -#define ABP1_RESET_OFFSET_MMC3 11 >> -#define ABP1_RESET_OFFSET_MMC2 10 >> -#define ABP1_RESET_OFFSET_MMC1 9 >> -#define ABP1_RESET_OFFSET_MMC0 8 >> -#define ABP1_RESET_OFFSET_MMC(n) (ABP1_RESET_OFFSET_MMC0 + (n)) >> +/* apb2 reset */ >> +#define APB2_RESET_UART_SHIFT (16) >> +#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) >> +#define APB2_RESET_TWI_SHIFT (0) >> +#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) >> >> #endif /* _SUNXI_CLOCK_SUN6I_H */ >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c >> index 0851d85..d6c051e 100644 >> --- a/drivers/mmc/sunxi_mmc.c >> +++ b/drivers/mmc/sunxi_mmc.c >> @@ -199,15 +199,11 @@ static int mmc_clk_io_on(int sdc_no) >> } >> >> /* config ahb clock */ >> - rval = readl(&ccm->ahb_gate0); >> - rval |= 1 << AHB_GATE_OFFSET_MMC(sdc_no); >> - writel(rval, &ccm->ahb_gate0); >> + setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); >> >> #if defined(CONFIG_SUN6I) >> /* unassert reset */ >> - rval = readl(SUN6I_ABP1_RESET_BASE); >> - rval |= 1 << ABP1_RESET_OFFSET_MMC(sdc_no); >> - writel(rval, SUN6I_ABP1_RESET_BASE); >> + setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no)); >> #endif >> >> /* config mod clock */ >> -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.