From: Marcus Cooper <codekip...@gmail.com>
All comments have been corrected to the format required by
the kernel.
Signed-off-by: Marcus Cooper <codekip...@gmail.com>
---
sound/soc/sunxi/spdif/sunxi_sndspdif.c | 94 ++++++++++++++++------------------
sound/soc/sunxi/spdif/sunxi_spdif.c | 61 +++++++++++-----------
sound/soc/sunxi/spdif/sunxi_spdma.c | 12 ++---
3 files changed, 80 insertions(+), 87 deletions(-)
diff --git a/sound/soc/sunxi/spdif/sunxi_sndspdif.c
b/sound/soc/sunxi/spdif/sunxi_sndspdif.c
index 8a13fd6..c5a8509 100644
--- a/sound/soc/sunxi/spdif/sunxi_sndspdif.c
+++ b/sound/soc/sunxi/spdif/sunxi_sndspdif.c
@@ -65,77 +65,71 @@ static void sunxi_sndspdif_shutdown(struct
snd_pcm_substream *substream)
mutex_unlock(&clk_lock);
}
-typedef struct __MCLK_SET_INF
-{
- __u32 samp_rate; // sample rate
- __u16 mult_fs; // multiply of smaple rate
-
- __u8 clk_div; // mpll division
- __u8 mpll; // select mpll, 0 - 24.576 Mhz, 1 - 22.5792 Mhz
+typedef struct __MCLK_SET_INF {
+ __u32 samp_rate; /* sample rate */
+ __u16 mult_fs; /* multiply of sample rate */
+ __u8 clk_div; /* mpll division */
+ __u8 mpll; /* select mpll, 0:24.576 Mhz, 1:22.5792 Mhz */
} __mclk_set_inf;
-typedef struct __BCLK_SET_INF
-{
- __u8 bitpersamp; // bits per sample
- __u8 clk_div; // clock division
- __u16 mult_fs; // multiplay of sample rate
-
+typedef struct __BCLK_SET_INF {
+ __u8 bitpersamp; /* bits per sample */
+ __u8 clk_div; /* clock division */
+ __u16 mult_fs; /* multiplay of sample rate */
} __bclk_set_inf;
-static __bclk_set_inf BCLK_INF[] =
-{
- // 16bits per sample
- {16, 4, 128}, {16, 6, 192}, {16, 8, 256},
- {16, 12, 384}, {16, 16, 512},
+static __bclk_set_inf BCLK_INF[] = {
+ /* 16bits per sample */
+ {16, 4, 128}, {16, 6, 192}, {16, 8, 256},
+ {16, 12, 384}, {16, 16, 512},
- //24 bits per sample
- {24, 4, 192}, {24, 8, 384}, {24, 16, 768},
+ /* 24 bits per sample */
+ {24, 4, 192}, {24, 8, 384}, {24, 16, 768},
- //32 bits per sample
- {32, 2, 128}, {32, 4, 256}, {32, 6, 384},
- {32, 8, 512}, {32, 12, 768},
+ /* 32 bits per sample */
+ {32, 2, 128}, {32, 4, 256}, {32, 6, 384},
+ {32, 8, 512}, {32, 12, 768},
- //end flag
- {0xff, 0, 0},
+ /* end flag */
+ {0xff, 0, 0},
};
-//TX RATIO value
-static __mclk_set_inf MCLK_INF[] =
-{
- //88.2k bitrate //2
- { 88200, 128, 2, 1}, { 88200, 256, 2, 1},
+/* TX RATIO value */
+static __mclk_set_inf MCLK_INF[] = {
+ /* 88.2k bitrate //2 */
+ { 88200, 128, 2, 1}, { 88200, 256, 2, 1},
- //22.05k bitrate //8
- { 22050, 128, 8, 1}, { 22050, 256, 8, 1},
- { 22050, 512, 8, 1},
+ /* 22.05k bitrate //8 */
+ { 22050, 128, 8, 1}, { 22050, 256, 8, 1},
+ { 22050, 512, 8, 1},
- // 24k bitrate //8
- { 24000, 128, 8, 0}, { 24000, 256, 8, 0}, { 24000, 512, 8, 0},
+ /* 24k bitrate //8 */
+ { 24000, 128, 8, 0}, { 24000, 256, 8, 0}, { 24000, 512, 8, 0},
- // 32k bitrate //2.048MHz 24/4 = 6
- { 32000, 128, 6, 0}, { 32000, 192, 6, 0}, { 32000, 384, 6, 0},
- { 32000, 768, 6, 0},
+ /* 32k bitrate //2.048MHz 24/4 = 6 */
+ { 32000, 128, 6, 0}, { 32000, 192, 6, 0}, { 32000, 384, 6, 0},
+ { 32000, 768, 6, 0},
- // 48K bitrate 3.072 Mbit/s 16/4 = 4
- { 48000, 128, 4, 0}, { 48000, 256, 4, 0}, { 48000, 512, 4, 0},
+ /* 48K bitrate 3.072Mbit/s 16/4 = 4 */
+ { 48000, 128, 4, 0}, { 48000, 256, 4, 0}, { 48000, 512, 4, 0},
- // 96k bitrate 6.144MHZ 8/4 = 2
- { 96000, 128 , 2, 0}, { 96000, 256, 2, 0},
+ /* 96k bitrate 6.144MHZ 8/4 = 2 */
+ { 96000, 128 , 2, 0}, { 96000, 256, 2, 0},
- //192k bitrate 12.288MHZ 4/4 = 1
- {192000, 128, 1, 0},
+ /* 192k bitrate 12.288MHZ 4/4 = 1 */
+ {192000, 128, 1, 0},
- //44.1k bitrate 2.8224MHz 16/4 = 4
- { 44100, 128, 4, 1}, { 44100, 256, 4, 1}, { 44100, 512, 4, 1},
+ /* 44.1k bitrate 2.8224MHz 16/4 = 4 */
+ { 44100, 128, 4, 1}, { 44100, 256, 4, 1}, { 44100, 512, 4, 1},
- //176.4k bitrate 11.2896MHZ 4/4 = 1
- {176400, 128, 1, 1},
+ /* 176.4k bitrate 11.2896MHZ 4/4 = 1 */
+ {176400, 128, 1, 1},
- //end flag 0xffffffff
- {0xffffffff, 0, 0, 0},
+ /* end flag 0xffffffff */
+ {0xffffffff, 0, 0, 0},
};
static s32 get_clock_divder(u32 sample_rate, u32 sample_width, u32 * mclk_div,
u32* mpll, u32* bclk_div, u32* mult_fs)
diff --git a/sound/soc/sunxi/spdif/sunxi_spdif.c
b/sound/soc/sunxi/spdif/sunxi_spdif.c
index 29c9116..9cc6264 100644
--- a/sound/soc/sunxi/spdif/sunxi_spdif.c
+++ b/sound/soc/sunxi/spdif/sunxi_spdif.c
@@ -68,53 +68,53 @@ void sunxi_snd_txctrl(struct snd_pcm_substream *substream,
int on)
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
}
- //soft reset SPDIF
+ /* soft reset SPDIF */
writel(0x1, sunxi_spdif.regs + SUNXI_SPDIF_CTL);
- //MCLK OUTPUT enable
+ /* MCLK OUTPUT enable */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_CTL);
reg_val |= SUNXI_SPDIF_CTL_MCLKOUTEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_CTL);
- //flush TX FIFO
+ /* flush TX FIFO */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_FCTL);
reg_val |= SUNXI_SPDIF_FCTL_FTX;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_FCTL);
- //clear interrupt status
+ /* clear interrupt status */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_ISTA);
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_ISTA);
- //clear TX counter
+ /* clear TX counter */
writel(0, sunxi_spdif.regs + SUNXI_SPDIF_TXCNT);
if (on) {
- //SPDIF TX ENBALE
+ /* SPDIF TX ENABLE */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
reg_val |= SUNXI_SPDIF_TXCFG_TXEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
- //DRQ ENABLE
+ /* DRQ ENABLE */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_INT);
reg_val |= SUNXI_SPDIF_INT_TXDRQEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_INT);
- //global enable
+ /* Global enable */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_CTL);
reg_val |= SUNXI_SPDIF_CTL_GEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_CTL);
} else {
- //SPDIF TX DISABALE
+ /* SPDIF TX DISABLE */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
reg_val &= ~SUNXI_SPDIF_TXCFG_TXEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
- //DRQ DISABLE
+ /* DRQ DISABLE */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_INT);
reg_val &= ~SUNXI_SPDIF_INT_TXDRQEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_INT);
- //global disable
+ /* Global disable */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_CTL);
reg_val &= ~SUNXI_SPDIF_CTL_GEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_CTL);
@@ -145,7 +145,8 @@ static int sunxi_spdif_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
reg_val |= SUNXI_SPDIF_FCTL_RXOM(3);
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_FCTL);
- if (!fmt) {//PCM
+ if (!fmt) {
+ /* PCM */
reg_val = 0;
reg_val |= (SUNXI_SPDIF_TXCHSTA0_CHNUM(2));
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
@@ -153,7 +154,8 @@ static int sunxi_spdif_set_fmt(struct snd_soc_dai *cpu_dai,
unsigned int fmt)
reg_val = 0;
reg_val |= (SUNXI_SPDIF_TXCHSTA1_SAMWORDLEN(1));
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
- } else { //non PCM
+ } else {
+ /* non PCM */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
reg_val |= SUNXI_SPDIF_TXCFG_NONAUDIO;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_TXCFG);
@@ -225,7 +227,7 @@ static int sunxi_spdif_trigger(struct snd_pcm_substream
*substream,
return ret;
}
-//freq: 1: 22.5792MHz 0: 24.576MHz
+/* freq: 1: 22.5792MHz 0: 24.576MHz */
static int sunxi_spdif_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
unsigned int freq, int dir)
{
@@ -262,7 +264,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
{
switch(div)
{
- //24KHZ
+ /* 24KHZ */
case 8:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0x6));
@@ -273,7 +275,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //32KHZ
+ /* 32KHZ */
case 6:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0x3));
@@ -284,7 +286,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //48KHZ
+ /* 48KHZ */
case 4:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0x2));
@@ -295,7 +297,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //96KHZ
+ /* 96KHZ */
case 2:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0xA));
@@ -306,7 +308,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //192KHZ
+ /* 192KHZ */
case 1:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0xE));
@@ -327,10 +329,10 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
}
- }else{ //22.5792MHz
+ } else { /* 22.5792MHz */
switch(div)
{
- //22.05khz
+ /* 22.05khz */
case 8:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0x4));
@@ -341,7 +343,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //44.1KHZ
+ /* 44.1KHZ */
case 4:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0x0));
@@ -352,7 +354,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //88.2khz
+ /* 88.2khz */
case 2:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0x8));
@@ -363,7 +365,7 @@ static int sunxi_spdif_set_clkdiv(struct snd_soc_dai
*cpu_dai, int div_id, int d
writel(reg_val,
sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA1);
break;
- //176.4KHZ
+ /* 176.4KHZ */
case 1:
reg_val =
readl(sunxi_spdif.regs + SUNXI_SPDIF_TXCHSTA0);
reg_val |=
(SUNXI_SPDIF_TXCHSTA0_SAMFREQ(0xC));
@@ -438,7 +440,7 @@ static int sunxi_spdif_suspend(struct snd_soc_dai *cpu_dai)
spdifregsave();
- //disable the module clock
+ /* disable the module clock */
clk_disable(spdif_moduleclk);
clk_disable(spdif_apbclk);
@@ -454,10 +456,10 @@ static int sunxi_spdif_resume(struct snd_soc_dai *cpu_dai)
u32 reg_val;
printk("[SPDIF]Enter %s\n", __func__);
- //disable the module clock
+ /* disable the module clock */
clk_enable(spdif_apbclk);
- //enable the module clock
+ /* enable the module clock */
clk_enable(spdif_moduleclk);
spdifregrestore();
@@ -509,7 +511,6 @@ static int __devinit sunxi_spdif_dev_probe(struct
platform_device *pdev)
if(sunxi_spdif.regs == NULL)
return -ENXIO;
- //spdif apbclk
spdif_apbclk = clk_get(NULL, "apb_spdif");
if(-1 == clk_enable(spdif_apbclk)){
printk("spdif_apbclk failed! line = %d\n", __LINE__);
@@ -517,10 +518,8 @@ static int __devinit sunxi_spdif_dev_probe(struct
platform_device *pdev)
spdif_pllx8 = clk_get(NULL, "audio_pllx8");
- //spdif pll2clk
spdif_pll2clk = clk_get(NULL, "audio_pll");
- //spdif module clk
spdif_moduleclk = clk_get(NULL, "spdif");
if(clk_set_parent(spdif_moduleclk, spdif_pll2clk)){
@@ -535,7 +534,7 @@ static int __devinit sunxi_spdif_dev_probe(struct
platform_device *pdev)
printk("open spdif_moduleclk failed! line = %d\n",
__LINE__);
}
- //global enbale
+ /* Global enbale */
reg_val = readl(sunxi_spdif.regs + SUNXI_SPDIF_CTL);
reg_val |= SUNXI_SPDIF_CTL_GEN;
writel(reg_val, sunxi_spdif.regs + SUNXI_SPDIF_CTL);
diff --git a/sound/soc/sunxi/spdif/sunxi_spdma.c
b/sound/soc/sunxi/spdif/sunxi_spdma.c
index 67aa30e..7a37174 100644
--- a/sound/soc/sunxi/spdif/sunxi_spdma.c
+++ b/sound/soc/sunxi/spdif/sunxi_spdma.c
@@ -46,12 +46,12 @@ static const struct snd_pcm_hardware sunxi_pcm_hardware = {
.rate_max = 192000,
.channels_min = 1,
.channels_max = 2,
- .buffer_bytes_max = 128*1024, //1024*1024 /* value must be
(2^n)Kbyte size */
- .period_bytes_min = 1024*4,//1024*4,
- .period_bytes_max = 1024*32,//1024*128,
- .periods_min = 4,//8,
- .periods_max = 8,//8,
- .fifo_size = 32,//32,
+ .buffer_bytes_max = 128*1024, /* value must be (2^n)Kbyte size */
+ .period_bytes_min = 1024*4,
+ .period_bytes_max = 1024*32,
+ .periods_min = 4,
+ .periods_max = 8,
+ .fifo_size = 32,
};
struct sunxi_runtime_data {
--
1.9.1
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