Does this look better? Any chance of getting PLL2 support in the near future since I obviously know very little about the A20 clocks?
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index bed74a9..a347eff 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -137,6 +137,10 @@ status = "okay"; }; + codec@1c22c00 { + status = "okay"; + }; + ir0: ir@01c21800 { pinctrl-names = "default"; pinctrl-0 = <&ir0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 263eb79..41a4ed4 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -327,6 +327,30 @@ clock-output-names = "ir1"; }; + i2s0_clk: clk@01c200b8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-clk"; + reg = <0x01c200b8 0x4>; + clocks = <&pll2 1>; + clock-output-names = "i2s0"; + }; + + ac97_clk: clk@01c200bc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-clk"; + reg = <0x01c200bc 0x4>; + clocks = <&pll2 1>; + clock-output-names = "ac97"; + }; + + spdif_clk: clk@01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 1>; + clock-output-names = "spdif"; + }; + usb_clk: clk@01c200cc { #clock-cells = <1>; #reset-cells = <1>; @@ -344,6 +368,30 @@ clock-output-names = "spi3"; }; + i2s1_clk: clk@01c200d8 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-clk"; + reg = <0x01c200d8 0x4>; + clocks = <&pll2 1>; + clock-output-names = "i2s1"; + }; + + i2s2_clk: clk@01c200dc { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-clk"; + reg = <0x01c200dc 0x4>; + clocks = <&pll2 1>; + clock-output-names = "i2s2"; + }; + + codec_clk: clk@01c20140 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20140 0x4>; + clocks = <&pll2 1>; + clock-output-names = "codec"; + }; + mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -807,6 +855,66 @@ clocks = <&osc24M>; #pwm-cells = <3>; }; + + spdif@1c21000 { + compatible = "allwinner,sun7i-a20-spdif"; + reg = <0x01C21000 0x20>; + interrupts = <0 13 4>; + clocks = <&apb0_gates 1>, <&spdif_clk>; + dmas = <&dma 0 2>, <&dma 0 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + ac97@1c21400 { + compatible = "allwinner,sun7i-a20-ac97"; + reg = <0x01C21400 0x20>; + interrupts = <0 14 4>; + clocks = <&apb0_gates 2>, <&ac97_clk>; + dmas = <&dma 0 5>, <&dma 0 5>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s0: i2s@1c22000 { + compatible = "allwinner,sun7i-a20-i2s"; + reg = <0x01C22000 0x20>; + interrupts = <0 16 4>; + clocks = <&apb0_gates 3>, <&i2s0_clk>; + dmas = <&dma 0 3>, <&dma 0 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s1: i2s@1c22400 { + compatible = "allwinner,sun7i-a20-i2s"; + reg = <0x01C22400 0x20>; + interrupts = <0 87 4>; + clocks = <&apb0_gates 4>, <&i2s1_clk>; + dmas = <&dma 0 4>, <&dma 0 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s2: i2s@1c24400 { + compatible = "allwinner,sun7i-a20-i2s"; + reg = <0x01C24400 0x20>; + interrupts = <0 90 4>; + clocks = <&apb0_gates 8>, <&i2s2_clk>; + dmas = <&dma 0 6>, <&dma 0 6>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + codec@1c22c00 { + compatible = "allwinner,sun7i-a20-codec"; + reg = <0x01C22c00 0x20>; + interrupts = <0 30 4>; + clocks = <&apb0_gates 0>, <&codec_clk>; + dmas = <&dma 0 19>, <&dma 0 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; ir0: ir@01c21800 { compatible = "allwinner,sun7i-a20-ir"; -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.