On Mon, Aug 18, 2014 at 5:36 PM, <selsin...@gmail.com> wrote: > On 17/08/14 21:18, jonsm...@gmail.com wrote: >> I think I found the bug, my sgtl5000 is happy now at lower clock >> speeds. I was missing a 'L' and a value got truncated to 32 bits. > > Sorry for the late reply, I guess we're in different timezones :) > > Yes, that seems to work here too, giving expected outputs at lower > frequencies. > > Noticeable that at higher frequencies there are large jumps, for > example it gets to 6MHz then jumps to 8MHz then to 24MHz > > period values to frequencies look like this > up to 83 24MHz > 84 - 104 8MHz > 105 - 145 6MHz > 146 - 187 4.8MHz > 188 - 229 4MHz > 230 - 270 3.4MHz > 271 - 312 3MHz
Thanks for checking this, that pattern is expected and the best the chip can do. But it does look like I have another round off error in there. You should have been able to make 12Mhz. I'll see if I can fix it. It is 24Mhz divided by 2,3,4,5,6,7,8..... Looks like some more of the math is off.. This is what the periods should be. 24Mhz 41.6ns 12Mhz 83.3ns 8Mhz 125ns 6Mhz 167ns 4.8Mhz 208ns 4Mhz 250ns 3.4Mhz 292ns 3Mhz 333ns Looks like an off-by-one error. Each frequency has the previous period's timing. That missing 12Mhz probably threw everything off. > > and carries on in similar fashion with the jumps becoming smaller > each time as frequency decreases. > > I didn't look at the code in detail, but presumably this is > just a an expected result of which prescaler and divisor are being > picked and the PWM not really being intended to be used at high > frequencies. > It gets much less noticable as you go below 1MHz. > > -- Jon Smirl jonsm...@gmail.com -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
