On Fri, Aug 22, 2014 at 09:54:12AM -0300, Emilio López wrote:
> El 21/08/14 a las 15:28, Luc Verhaegen escibió:
>> On Thu, Aug 21, 2014 at 04:21:16AM +0200, Luc Verhaegen wrote:
>>>
>>> My test CRT is refusing to show 640x480 though, so while i diligently
>>> tested through the edges of the ranges (both of the internal loop, as
>>> of the external divider), i did mess something else up :)
>>>
>>> Ooh, that poor monitor, will it survive its 13th year? ;)
>>
>> Rounding error:
>>      clk_set_rate(lcdc->clock_ch1_s2, frequency_result / divider);
>>
>> If you do not do this beforehand, you will usually get a lower divider
>> actually set:
>>      frequency_result += divider - 1;
>
> So you're doing DIV_ROUND_UP(frequency_result, divider)
>
>> Thanks to the sunxi clock code thinking it should be higher level than
>> is useful or sensible.
>
> Maybe you need a different rounding policy, like to closest instead of  
> <=. I haven't looked at the code though, so feel free to ignore me if  
> I'm talking nonsense :)

The issue exists in disp as well.

This is how the dotclock setup works: we have an actual PLL (3/7), where 
we have set a given multiple of 3MHz, and we use that to drive the lcdc 
tcon1 clock. We can then either use that PLL clock directly or double it 
when selecting the source, and afterwards apply a divider from 1-16.

The allwinner code allows us to set a frequency for PLL3, a parent 
(PLL3/7, doubled or not) for the dotclock (lcdc tcon1), and then a 
frequency for the dotclock. Save from setting the register directly 
(which would be very sensible here), we do not get to set the divider 
directly: we only get to set the target frequency. Hence the rounding 
error.

It's yet another one of those cases where "just map the hardware as-is" 
would've saved everyones bacon.

Anyway, this code is vastly different on mainline, so i hope that there 
at least i get to set multipliers and dividers directly, as i really do 
know what's best here.

Luc Verhaegen.

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