On Thu, Aug 20, 2015 at 02:19:46PM -0000, Michal Suchanek wrote: > Only SPI0 is enabled. The schematic denotes it as the only SPI bus. > Other SPI pins are reserved for different peripherals. > > Signed-off-by: Michal Suchanek <hramr...@gmail.com>
What device is connected to the other end?
> ---
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> index 39a51d5..9861304 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> @@ -198,6 +198,13 @@
> status = "okay";
> };
>
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins_a>,
> + <&spi0_cs0_pins_a>;
> + status = "okay";
> +};
> +
You should probably add an alias to that bus too.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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