OK let me rephrase my issue . This what I understood so far from the bsp driver and the manual.
CSI0 module for example has 3 channels and in each channel there is 3 FIFOs, each FIFO has 2 buffers( A & B). The output of the buffer(depends on the configuration ) will be available at the memory address(DRAM range) which is set by the output buffer address register. For me this looks like a DMA controller role which is similar to imx3 IPU !. My question. Is the main DMA controller has access to the CSI output buffers. And if not can I implement part of this driver using dma engin framework. Thank you in advance. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
