在 2017-05-05 10:34，Yong 写道：
V3S's usb otg device reset bit should be 24, not 23
Could you add a "." here?
And you should contain a Signed-Off-By line here.
Reviewed-By: Icenowy Zheng <icen...@aosc.io>
(You can add this line to the end of the next version of your patch)
Please read Documentation/process/submitting-patches.rst first before
you
sending a patch. (Chinese translation available at
Documentation/process/submitting-patches.rst)
And please use your real name as the git commiter and the mail sender.
Please send this patch to the following people: (ignore things in () )
Maxime Ripard <maxime.rip...@free-electrons.com>
(maintainer:ARM/Allwinner sunXi SoC support)
Chen-Yu Tsai <w...@csie.org> (maintainer:ARM/Allwinner sunXi SoC
support)
And these mailing lists:
linux-arm-ker...@lists.infradead.org (moderated list:ARM/Allwinner sunXi
SoC support)
linux-...@vger.kernel.org (open list:COMMON CLK FRAMEWORK)
linux-ker...@vger.kernel.org (open list)
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index e58706b..6297add 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -537,7 +537,7 @@ static CLK_FIXED_FACTOR(pll_periph0_2x_clk,
"pll-periph0-2x",
[RST_BUS_EMAC] = { 0x2c0, BIT(17) },
[RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
[RST_BUS_SPI0] = { 0x2c0, BIT(20) },
- [RST_BUS_OTG] = { 0x2c0, BIT(23) },
+ [RST_BUS_OTG] = { 0x2c0, BIT(24) },
[RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
[RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
--
1.8.3.1
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