On Thu, May 9, 2019 at 4:18 PM Kamps, John-Eric <john-eric.ka...@honeywell.com> wrote: > > Hi all > > I have an Allwinner A64 based device and I wanted to bring the LVDS Display > to live. > http://linux-sunxi.org/Honeywell_VDP7 > > Attached is the patch for Jagan Tekis kernel from > https://github.com/amarula/linux-amarula.git > Version: 3fcf0ebf8263377172da3ad0628c67e411a58831 > > I added the LVDS pins to the sun50i-a64.dtsi: > lcd_lvds_pins: lcd-lvds-pins { > pins = "PD12", "PD13", "PD14", "PD15", "PD16", > "PD17", "PD18", "PD19", "PD20", "PD21"; > function = "lvds0"; > }; > > And I used the information from sun8i-a83t-tbs-a711.dts with changed values > to write my own connection: > + panel { > + compatible = "tbs,a711-panel", "panel-lvds"; > + backlight = <&backlight>; > + power-supply = <®_dc1sw>; > + > + width-mm = <154>; > + height-mm = <86>; > + data-mapping = "vesa-24"; > + > +/* reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>;*/ /* RST (PD24) */ > + > + panel-timing { > + /* 1024x600 @60Hz */ > + clock-frequency = <51450000>; > + hactive = <1024>; > + vactive = <600>; > + hsync-len = <8>; > + hfront-porch = <156>; > + hback-porch = <156>; > + vfront-porch = <16>; > + vback-porch = <16>; > + vsync-len = <6>; > +// de-active = <0>; > +// hsync-active = <1>; > +// vsync-active = <1>; > + }; > + > + port { > + panel_input: endpoint { > + remote-endpoint = <&tcon0_out_lcd>; > + }; > + }; > + }; > And for TCON connection > +&tcon0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&lcd_lvds_pins>; > +}; > + > +&tcon0_out { > + tcon0_out_lcd: endpoint@0{ > + reg = <0>; > + remote-endpoint = <&panel_input>; > + }; > > I will get a framebuffer device. The backlight is working and I can change > the brightness. The panal-lvds is used and the clock looks that they will be > generated in the attached bootlog. > I also added some additional debug outputs to be aware, that the functions > are called. Looks also fine for me. > > I checked the sunxi-lvds source file and compared the lvds register settings > with the voltage levels on the pins. They are identical and looking fine for > me. I checked with an Osciloscope the signals but they are statical. No > changes on them. I also checked the reset line, voltages and so on, they are > correct that with signal input all should work. > > My current thinking is, that there are something wrong with the dts tcon > connection. I checked also to use reg 1 (MIPI) and not reg 0, but then I will > get no framebuffer and some dct warnings that the MIPI Display is only > connected in one direction. > > I'm going deeper and deeper in the dts writing and find a lot. But lvds and > allwinner devices is not really documented anywhere. > Did someone has an idea what could be wrong?
Pipeline seems fine to me quick look, and lvds connector gets detected in the log. I'm suspecting about pixel clock with respective lvds divider values Possible checks. 01. Try the bsp first, since we don't have any kind of reference documents. 02: Identify the working pixel clock rates along with dividers 03: Better get the regmap of tcon0 and other sequence for cross verification. Jagan. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAMty3ZA5RYZtLLrRpEjrhoigh6B3t%2BLX7H9%3DA8Oi51agc4DpLg%40mail.gmail.com. For more options, visit https://groups.google.com/d/optout.
