Hi. Thanks for the sample code. I read the register (Attached file with comments) and compared them with the Allwinner User Manual V1.1
Summary Clock: Video0 = 24MHz*99/8=297MHz MIPI based on Video0 = 297MHz*3*2/5=356,4MHz Then the pixel clock is 356,4MHz/7=50,914MHz Requested is 51,45MHz --> Sounds OK for me and is the same in the debug output: sun4i_dclk_round_rate: ideal = 360150000, rounded = 356400000, div = 7 sun4i_dclk_round_rate: div = 7 rate = 50914285 Summary tcon0: TCON0 Control: En, normal, sync+DE, 1E=TCON start delay ,src=DE0 TCON0 Clock: dclk, dclk1, dclk2, dclkm2 --> on; DCLK-DIV=7 --> >6 --> OK x=1023+1, y=599+1 HT=1343+1, HBP=163+1 VT=1276, VBP=21+1 HSPW=0+1 , VSPW=0+1 HV Panal Interface: 24Bit, RGB LVDS-Panel: Enable, normal, NS-Mode, 24Bit, debug off, lvds mode0, LVDS_CLK_SEL --> TCON_CLK, polarity normal polarity: normal output, use DCLK0, IO2/3 = not invert, IO1/0 = invert, data normal polarity --> It sounds strange for me, that channel 0 and 1 are inverted and the others not. io trigger reg: RGB endian normal, IO0-3 enabled, data enabled LVDS ANA0 is like expected and the same what the kernel will set up. Measured voltage levels are the same like configured. One thing is strange. In LVDS-Panel Interface Register (0x084) is bit 20 TCON0_LVDS_Clk_Sel=1. And this means TCON0_CLK and not MIPI_CLK source. From my understanding the MIPI clock, which is based on the video0 clock, has the correct frequency and should be normally used, or? I will search for them in the driver and check it. -----Ursprüngliche Nachricht----- Von: Priit Laes [mailto:pl...@plaes.org] Gesendet: Dienstag, 21. Mai 2019 10:39 An: Kamps, John-Eric Cc: ja...@amarulasolutions.com; linux-sunxi@googlegroups.com Betreff: [External] Re: [linux-sunxi] Re: Bringing LVDS on A64 (VDP7) to work On Tue, May 21, 2019 at 07:24:32AM +0000, Kamps, John-Eric wrote: > Hi Jagan > > >Possible checks. > > >01. Try the bsp first, since we don't have any kind of reference documents. > OK I will compare them > > >02: Identify the working pixel clock rates along with dividers > I will check the kernel log from the original device. > > >03: Better get the regmap of tcon0 and other sequence for cross > >verification. > How can I get these values? Is there a bash command, or debugging, log > output, syslog interface file? Using busybox `devmem` applet or devmem2 utility. If you're using Armbian/Debian just `apt install busybox`. And sample usage of the devmem applet I used to debug hdmi issues on A20: [snip] #! /bin/bash function dump { base=$1 size=$2 for((i=0;i<$size;i=i+4)) ; do addr=$(($base + $i)) data=$(busybox devmem $addr) echo $(printf '%#x: %s' $addr $data) done } function f { dump $(( $1 )) $(( $2 )) } # XXX: These are A20 addresses and block sizes # tcon0 f 0x01c0c000 0x1000 # ccu f 0x01c20000 0x400 [/snip] -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/SN6PR07MB5199343AED7B618AF374F416AB070%40SN6PR07MB5199.namprd07.prod.outlook.com. For more options, visit https://groups.google.com/d/optout.
tcon0 0x1c0c000: 0x80000000 --> Enable + TCON0 0x1c0c004: 0xC8000000 --> TCON0/1_Vb_Int_En 0x1c0c008: 0x00000000 0x1c0c00c: 0x00000000 --> NA 0x1c0c010: 0x00000000 --> FRM disabled 0x1c0c014: 0x11111111 --> FRM Seed Reg0 0x1c0c018: 0x11111111 0x1c0c01c: 0x11111111 0x1c0c020: 0x11111111 0x1c0c024: 0x11111111 0x1c0c028: 0x11111111 0x1c0c02c: 0x01010000 --> FRM Table Reg0 0x1c0c030: 0x15151111 0x1c0c034: 0x57575555 0x1c0c038: 0x7F7F7777 0x1c0c03c: 0x00000000 --> 3D FIFO off 0x1c0c040: 0x800001E0 --> TCON0 Control: En, normal, sync+DE, 1E=TCON start delay ,src=DE0 0x1c0c044: 0x80000007 --> TCON0 Clock: dclk, dclk1, dclk2, dclkm2 --> on; DCLK-DIV=7 --> >6 --> OK 0x1c0c048: 0x03FF0257 --> x=1023+1, y=599+1 0x1c0c04c: 0x053F00A3 --> HT=1343+1, HBP=163+1 0x1c0c050: 0x04FC0015 --> VT=1276, VBP=21+1 0x1c0c054: 0x00000000 --> HSPW=0+1 , VSPW=0+1 0x1c0c058: 0x00000000 --> HV Panal Interface: 24Bit, RGB 0x1c0c05c: 0x00000000 --> NA 0x1c0c060: 0x00000000 --> CPU Panal Interface: for cpu interface displays 0x1c0c064: 0x00000000 0x1c0c068: 0x00000000 0x1c0c06c: 0x00000000 0x1c0c070: 0x00000000 0x1c0c074: 0x00000000 0x1c0c078: 0x00000000 0x1c0c07c: 0x00000000 0x1c0c080: 0x00000000 0x1c0c084: 0x8010001F --> LVDS-Panel: Enable, normal, NS-Mode, 24Bit, debug off, lvds mode0, LVDS_CLK_SEL --> TCON_CLK, polarity normal 0x1c0c088: 0x03000000 --> polarity: normal output, use DCLK0, IO2/3 = not invert, IO1/0 = invert, data normal polarity 0x1c0c08c: 0xE0000000 --> io trigger reg: RGB endian normal, IO0-3 enabled, data enabled 0x1c0c090: 0x00000000 0x1c0c094: 0x00000000 0x1c0c098: 0x00000000 0x1c0c09c: 0x00000000 0x1c0c0a0: 0x00000000 0x1c0c0a4: 0x00000000 0x1c0c0a8: 0x00000000 0x1c0c0ac: 0x00000000 0x1c0c0b0: 0x00010001 0x1c0c0b4: 0x00000000 0x1c0c0b8: 0x00000000 0x1c0c0bc: 0x00000000 0x1c0c0c0: 0x00000000 0x1c0c0c4: 0x00000000 0x1c0c0c8: 0x00000000 0x1c0c0cc: 0x00000000 0x1c0c0d0: 0x00000000 0x1c0c0d4: 0x00000000 0x1c0c0d8: 0x00000000 0x1c0c0dc: 0x00000000 0x1c0c0e0: 0x00000000 0x1c0c0e4: 0x00000000 0x1c0c0e8: 0x00000000 0x1c0c0ec: 0x00000000 0x1c0c0f0: 0x00000000 0x1c0c0f4: 0xFFFFFFFF 0x1c0c0f8: 0x00000000 0x1c0c0fc: 0x20000000 0x1c0c100: 0x00000000 --> CEU Control: bypass 0x1c0c104: 0x00000000 0x1c0c108: 0x00000000 0x1c0c10c: 0x00000000 0x1c0c110: 0x00000000 --> CEU Coeff Mul0: Value=0 0x1c0c114: 0x00000000 0x1c0c118: 0x00000000 0x1c0c11c: 0x00000000 --> CEU Coeff Add: Value=0 0x1c0c120: 0x00000000 0x1c0c124: 0x00000000 0x1c0c128: 0x00000000 0x1c0c12c: 0x00000000 0x1c0c130: 0x00000000 0x1c0c134: 0x00000000 0x1c0c138: 0x00000000 0x1c0c13c: 0x00000000 0x1c0c140: 0x00000000 --> CEU Coeff Range: Values=0 0x1c0c144: 0x00000000 0x1c0c148: 0x00000000 0x1c0c14c: 0x00000000 0x1c0c150: 0x00000000 0x1c0c154: 0x00000000 0x1c0c158: 0x00000000 0x1c0c15c: 0x00000000 0x1c0c160: 0x00000000 --> CPU Panel Trigger0 Reg: blockspace=0; blocksize=0 0x1c0c164: 0x00000000 --> CPU Panel Trigger1 Reg: 0x1c0c168: 0x00200000 --> CPU Panel Trigger2 Reg: Tdly=32+1; ecc_fifo, auto sync 0x1c0c16c: 0x00000000 --> CPU Panel Trigger3 Reg: disabled 0x1c0c170: 0x00000000 --> CPU Panel Trigger4 Reg: plug_mode=disabled 0x1c0c174: 0x00000000 --> CPU Panel Trigger5 Reg 0x1c0c178: 0x00000000 0x1c0c17c: 0x00000000 0x1c0c180: 0x00000000 --> Color Map Reg: bypass 0x1c0c184: 0x00000000 0x1c0c188: 0x00000000 0x1c0c18c: 0x00000000 0x1c0c190: 0x00000000 --> Color Map odd Line0: in_be0 0x1c0c194: 0x00000000 0x1c0c198: 0x00000000 0x1c0c19c: 0x00000000 0x1c0c1a0: 0x00000000 0x1c0c1a4: 0x00000000 0x1c0c1a8: 0x00000000 0x1c0c1ac: 0x00000000 0x1c0c1b0: 0x00000000 0x1c0c1b4: 0x00000000 0x1c0c1b8: 0x00000000 0x1c0c1bc: 0x00000000 0x1c0c1c0: 0x00000000 0x1c0c1c4: 0x00000000 0x1c0c1c8: 0x00000000 0x1c0c1cc: 0x00000000 0x1c0c1d0: 0x00000000 0x1c0c1d4: 0x00000000 0x1c0c1d8: 0x00000000 0x1c0c1dc: 0x00000000 0x1c0c1e0: 0x00000000 0x1c0c1e4: 0x00000000 0x1c0c1e8: 0x00000000 0x1c0c1ec: 0x00000000 0x1c0c1f0: 0x00000020 --> Safe Period Register: safe at ecc_fifo_curr_num 0x1c0c1f4: 0x00000000 0x1c0c1f8: 0x00000000 0x1c0c1fc: 0x00000000 0x1c0c200: 0x00000000 0x1c0c204: 0x00000000 0x1c0c208: 0x00000000 0x1c0c20c: 0x00000000 0x1c0c210: 0x00000000 0x1c0c214: 0x00000000 0x1c0c218: 0x00000000 0x1c0c21c: 0x00000000 0x1c0c220: 0xC1F40320 --> LVDS ANA0: lvds0: en_mb=on, en_ldo=on, en_drvc=on, en_drv=on, dram_test_clk=off, reg_c=350mV, reg_den(c)=off, reg_v=1,43V, reg_pd=0x10 0x1c0c224: 0x00000000 0x1c0c228: 0x00000000 0x1c0c22c: 0x00000000 0x1c0c230: 0x00000000 ccu 0x1c20000: 0x90001521 0x1c20004: 0x00000000 0x1c20008: 0x91000D0D 0x1c2000c: 0x00000000 0x1c20010: 0x93006207 --> Video0 Control Register: Enabled, manual mode, locked, PLL Output=297MHz, integer mode, PLL SDM disabled, factor_n=98+1, factor_m=7+1 --> 24MHz*99/8=297MHz 0x1c20014: 0x00000000 0x1c20018: 0x03006207 0x1c2001c: 0x00000000 0x1c20020: 0x00001000 0x1c20024: 0x00000000 0x1c20028: 0x90041811 0x1c2002c: 0x00041811 0x1c20030: 0x03006207 0x1c20034: 0x00000000 0x1c20038: 0x93001700 0x1c2003c: 0x00000000 0x1c20040: 0x90C00214 --> MIPI Control Register: Enabled, locked, integer, pll output*1, PLL input*6.25, LDO0/1 on, source=video0 pll, div5, mipi mode, factor_n=2+1, factor_k=1+1, pre_div_m=4+1 --> 297MHz*3*2/5=356,4MHz 0x1c20044: 0x03001300 0x1c20048: 0x93006207 0x1c2004c: 0x90003700 0x1c20050: 0x00020102 0x1c20054: 0x00003180 0x1c20058: 0x01000000 0x1c2005c: 0x00000001 0x1c20060: 0x33800240 0x1c20064: 0x00101018 0x1c20068: 0x00000021 0x1c2006c: 0x00010003 0x1c20070: 0x00000000 0x1c20074: 0x00000000 0x1c20078: 0x00000000 0x1c2007c: 0x00000000 0x1c20080: 0x00000000 0x1c20084: 0x00000000 0x1c20088: 0x0100000B 0x1c2008c: 0x8100000B 0x1c20090: 0x01000005 0x1c20094: 0x00000000 0x1c20098: 0x00000000 0x1c2009c: 0x00000000 0x1c200a0: 0x00000000 0x1c200a4: 0x00000000 0x1c200a8: 0x00000000 0x1c200ac: 0x00000000 0x1c200b0: 0x00000000 0x1c200b4: 0x00000000 0x1c200b8: 0x00000000 0x1c200bc: 0x00000000 0x1c200c0: 0x00000000 0x1c200c4: 0x00000000 0x1c200c8: 0x00000000 0x1c200cc: 0x00030303 0x1c200d0: 0x00000000 0x1c200d4: 0x00000000 0x1c200d8: 0x00000000 0x1c200dc: 0x00000000 0x1c200e0: 0x00000000 0x1c200e4: 0x00000000 0x1c200e8: 0x00000000 0x1c200ec: 0x00000000 0x1c200f0: 0x00000000 0x1c200f4: 0x80100000 0x1c200f8: 0xCCCA0000 0x1c200fc: 0x80000000 0x1c20100: 0x00000000 0x1c20104: 0x81000000 --> DE Clock Gating --> on, source=PLL_DE 0x1c20108: 0x00000000 0x1c2010c: 0x00000000 0x1c20110: 0x00000000 0x1c20114: 0x00000000 0x1c20118: 0x80000000 --> TCON0 Clock Gating: on, source=PLL_MIPI 0x1c2011c: 0x00000000 0x1c20120: 0x00000000 0x1c20124: 0x00000000 0x1c20128: 0x00000000 0x1c2012c: 0x00000000 0x1c20130: 0x00000000 0x1c20134: 0x00000000 0x1c20138: 0x00000000 0x1c2013c: 0x00000000 0x1c20140: 0x80000000 0x1c20144: 0x00000000 0x1c20148: 0x00000000 0x1c2014c: 0x00000000 0x1c20150: 0x00000000 0x1c20154: 0x00000000 0x1c20158: 0x00000000 0x1c2015c: 0x81000002 0x1c20160: 0x00000000 0x1c20164: 0x00000000 0x1c20168: 0x00000000 0x1c2016c: 0x00000000 0x1c20170: 0x00000000 0x1c20174: 0x00000000 0x1c20178: 0x00000000 0x1c2017c: 0x00000000 0x1c20180: 0x00000000 0x1c20184: 0x00000000 0x1c20188: 0x00000000 0x1c2018c: 0x00000000 0x1c20190: 0x00000000 0x1c20194: 0x00000000 0x1c20198: 0x00000000 0x1c2019c: 0x00000000 0x1c201a0: 0x80000000 0x1c201a4: 0x00000000 0x1c201a8: 0x00000000 0x1c201ac: 0x00000000 0x1c201b0: 0x80000000 0x1c201b4: 0x00000000 0x1c201b8: 0x00000000 0x1c201bc: 0x00000000 0x1c201c0: 0x00000000 0x1c201c4: 0x00000000 0x1c201c8: 0x00000000 0x1c201cc: 0x00000000 0x1c201d0: 0x00000000 0x1c201d4: 0x00000000 0x1c201d8: 0x00000000 0x1c201dc: 0x00000000 0x1c201e0: 0x00000000 0x1c201e4: 0x00000000 0x1c201e8: 0x00000000 0x1c201ec: 0x00000000 0x1c201f0: 0x00000000 0x1c201f4: 0x00000000 0x1c201f8: 0x00000000 0x1c201fc: 0x00000000 0x1c20200: 0x000000FF 0x1c20204: 0x000000FF 0x1c20208: 0x00000000 0x1c2020c: 0x00000000 0x1c20210: 0x00000000 0x1c20214: 0x00000000 0x1c20218: 0x00000000 0x1c2021c: 0x10100010 0x1c20220: 0x08100200 0x1c20224: 0x10100000 0x1c20228: 0x10100000 --> Video0 Bias 0x1c2022c: 0x10100000 0x1c20230: 0x81104000 0x1c20234: 0x10100010 0x1c20238: 0x10100000 0x1c2023c: 0x10100000 0x1c20240: 0xF8100400 0x1c20244: 0x10100000 0x1c20248: 0x10100000 0x1c2024c: 0x10010000 0x1c20250: 0x0A10103D 0x1c20254: 0x00000000 0x1c20258: 0x00000000 0x1c2025c: 0x00000000 0x1c20260: 0x14880008 0x1c20264: 0x00000000 0x1c20268: 0x00000000 0x1c2026c: 0x00000000 0x1c20270: 0x8A002000 --> MIPI Tuning, VCO Gain Control=on 0x1c20274: 0x00000000 0x1c20278: 0x00000000 0x1c2027c: 0x00000000 0x1c20280: 0x00000000 0x1c20284: 0xC000AC02 0x1c20288: 0x00000000 --> Video Pattern Control 0x1c2028c: 0x00000000 0x1c20290: 0x00000000 0x1c20294: 0x00000000 0x1c20298: 0x00000000 0x1c2029c: 0x00000000 0x1c202a0: 0x00000000 --> MIPI Pattern Control 0x1c202a4: 0x00000000 0x1c202a8: 0x00000000 0x1c202ac: 0x00000000 0x1c202b0: 0x00000000 0x1c202b4: 0x00000000 0x1c202b8: 0x00000000 0x1c202bc: 0x00000000 0x1c202c0: 0x33804240 0x1c202c4: 0x00101019 0x1c202c8: 0x00000001 0x1c202cc: 0x00000000 0x1c202d0: 0x00000001 0x1c202d4: 0x00000000 0x1c202d8: 0x001D0003 0x1c202dc: 0x00000000 0x1c202e0: 0x00000000 0x1c202e4: 0x00000000 0x1c202e8: 0x00000000 0x1c202ec: 0x00000000 0x1c202f0: 0x00000007 0x1c202f4: 0x00000000 0x1c202f8: 0x00000000 0x1c202fc: 0x00000000 0x1c20300: 0x00000000 0x1c20304: 0x00000000 0x1c20308: 0x00000000 0x1c2030c: 0x00000000 0x1c20310: 0x00000000 0x1c20314: 0x00000000 0x1c20318: 0x00000000 0x1c2031c: 0x00000000 0x1c20320: 0x00001FFF
