On Mon, Dec 26, 2011 at 04:44:41PM +0530, Alok Chauhan wrote:
> From: Alok Chauhan <[email protected]>
>
> In NACK error condition, I2C controller violates clock-to-data setup
> time before stop. In Software, because of this reset of controller is
> happening before I2C controller could complete STOP condition.
>
> Added delay of 2 clock period before reset the controller in case of
> NACK error.
>
> Signed-off-by: Alok Chauhan <[email protected]>
> ---
> Instead of setting constant value for delay as was in previous patch,
> now in the current modification delay will be calculated based on clock
> frequency of the bus.
> drivers/i2c/busses/i2c-tegra.c | 8 ++++++++
> 1 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-tegra.c
> b/drivers/i2c/busses/i2c-tegra.c index 6381604..62e197c 100644
> --- a/drivers/i2c/busses/i2c-tegra.c
> +++ b/drivers/i2c/busses/i2c-tegra.c
> @@ -517,6 +517,14 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev
> *i2c_dev,
> if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
> return 0;
>
> + /*
> + * In NACK error condition resetting of I2C controller happens
> + * before STOP condition is properly completed by I2C controller,
> + * so wait for 2 clock cycle to complete STOP condition.
> + */
> + if (i2c_dev->msg_err == I2C_ERR_NO_ACK)
> + udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
> +
>Is a delay here good, would it be better to sleep so that some other process
>can gain cpu time?
We mostly used 100 khz i2c clock frequency and delay in that case will be 20
usec. Would it be
ok to sleep for such a smaller time? Won't it increase any other overhead?
tegra_i2c_init(i2c_dev);
> if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
> if (msg->flags & I2C_M_IGNORE_NAK)
> --
> 1.7.4.1
>
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--
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