On Fri, Mar 30, 2012 at 04:59:56PM -0600, Stephen Warren wrote: > From: Stephen Warren <[email protected]> > > Tegra20 and Tegra30 share the same register layout within registers, but > the addresses of the registers is a little different. Fix the driver to > cope with this. > > @@ -333,6 +336,26 @@ static struct irq_chip tegra_gpio_irq_chip = { > #endif > }; > > +struct tegra_gpio_soc_config { > + u32 bank_stride; > + u32 upper_offset; > +}; > + > +static struct tegra_gpio_soc_config tegra20_gpio_config = { > + .bank_stride = 0x80, > + .upper_offset = 0x800, > +}; > + > +static struct tegra_gpio_soc_config tegra30_gpio_config = { > + .bank_stride = 0x100, > + .upper_offset = 0x80, > +};
Hmm. I wonder if this would be better to just describe in the device tree bindings for the gpio controller? Perhaps split the reg property in a higher and lower to take care of the offset, and add a nvidia,bank-stride=<x> property? -Olof -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
