On 11/20/2015 10:11 AM, Jon Hunter wrote: > The _clk_disable_pll() function will attempt to place a PLL into bypass > if the TEGRA_PLL_BYPASS is specified for the PLL and then disable the PLL > by clearing the enable bit. To place the PLL into bypass, the bypass bit > needs to be set and not cleared. Fix this by setting the bypass bit and > not clearing it. > > Signed-off-by: Jon Hunter <jonath...@nvidia.com> > --- > drivers/clk/tegra/clk-pll.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > index d6d4ecb88e94..e5aa9c87df4c 100644 > --- a/drivers/clk/tegra/clk-pll.c > +++ b/drivers/clk/tegra/clk-pll.c > @@ -312,7 +312,7 @@ static void _clk_pll_disable(struct clk_hw *hw) > > val = pll_readl_base(pll); > if (pll->params->flags & TEGRA_PLL_BYPASS) > - val &= ~PLL_BASE_BYPASS; > + val |= PLL_BASE_BYPASS; > val &= ~PLL_BASE_ENABLE; > pll_writel_base(val, pll); > >
Good catch. Acked-by: Rhyland Klein <rkl...@nvidia.com> -- nvpublic -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
