On Wed, 2 Apr 2025 at 23:00, Herbert Xu <[email protected]> wrote:
>
> There is no fallback implementation of flush_dcache_range for the
> architectures that don't need it.
Yeah, that literally looks like an oversight.
Probably because nobody needed it - or people didn't realize it was an
option and did the "loop over each page by hand" as in your example.
So yeah, I think it would be good to just expose flush_dcache_range()
as a dummy empty function in <asm-generic/cacheflush.h>, with the
usual "if the architecture defines this, that will override it" rule.
However, part of the problem is likely just unclear semantics. Because
the existing flush_cache_range() is about pure virtual caches and how
they need to be flushed before the TLB is flushed.
Also about D$ aliasing, but there isn't necessarily any TLB issues.
Honestly, I'd personally be perfectly fine saying "nobody sane cares,
and if your D$ isn't coherent, your perf mmap won't work".
Linus
