> The earlier multinop patching is not quite safe because the cross > modified CPU could be already executing on a later nop when the > cross patching occurs. The Intel SDM allows cross modification > by larger stores as long as they are aligned. AMD has a similar > guarantee. > > Support GCC function-entry patch sites is the main motivation for > multinop, and these sites are always aligned. > > So enforce 8 bytes alignment of the multinop and use a safe RMW 8 byte store > to overwrite the 5 byte sequence. This assumes that the code is not > changing in parallel, but if that happens cross modification safety > is probably the smallest of the issues. > > Assisted-by: omp:gpt-5.6-luna > Signed-off-by: Andi Kleen <[email protected]>
Sashiko has reviewed this patch and found no issues. It looks great! -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=9
