On Wed, 14 Oct 2026 17:44:13 +0800, Xiaofeng Yuan <[email protected]> wrote: > A breakpoint trap taken in the middle of an LR/SC sequence clears the > load reservation, so an SC following the probed instruction always fails > and the enclosing retry loop re-enters the breakpoint, livelocking the > CPU. This series makes the RISC-V kprobes implementation reject probes > placed on an LR/SC instruction or between them, following arm64's > approach for its equivalent exclusive load/store instructions. >
Please do NOT reply new version against the previous thread. It is not easy to find a new version in the message list. Thanks, -- Masami Hiramatsu (Google) <[email protected]>
