A breakpoint trap taken in the middle of an LR/SC sequence clears the load reservation, so an SC following the probed instruction always fails and the enclosing retry loop re-enters the breakpoint, livelocking the CPU. This series makes the RISC-V kprobes implementation reject probes placed on an LR/SC instruction or between them, following arm64's approach for its equivalent exclusive load/store instructions.
Changes since v5: - Fix a dangling stack pointer in the KUnit test: a probe that was expected to be rejected but was unexpectedly registered stayed on a stack-allocated kprobe. - Add Acked-by: Masami Hiramatsu to the implementation patch. - Annotate that test_kprobes_lrsc() is never executed and that reject[] must match the length of test_kprobes_lrsc_offsets[]. Verified by cross-compiling for RISC-V and running the kprobes KUnit test in QEMU (ok 2 kprobes_riscv). Xiaofeng Yuan (2): riscv: kprobes: reject probes inside LR/SC sequences riscv: kprobes: add KUnit test for LR/SC sequence rejection arch/riscv/include/asm/insn.h | 33 ++++++++++ arch/riscv/kernel/probes/decode-insn.c | 2 + arch/riscv/kernel/probes/kprobes.c | 63 +++++++++++++++---- .../kernel/tests/kprobes/test-kprobes-asm.S | 30 +++++++++ .../riscv/kernel/tests/kprobes/test-kprobes.c | 31 +++++++++ .../riscv/kernel/tests/kprobes/test-kprobes.h | 3 + 6 files changed, 150 insertions(+), 12 deletions(-) -- 2.34.1
