David Brownell wrote:
I'm not quite clear what the problem is here -- latch-without-clear?
That's what it sounds like: this chip design didn't really consider how certain USB features get used, and endpoint halts may need to be added to the list (with configs and altsettings).
You may need to fail the set_halt() method with -EOPNOTSUPP except for ep0. The gadgetfs code goes down that path for ep0 "delayed response" modes; you might not have had a chance to test with that yet. (I'm sure hoping ep0 protocol stalls work!)
Can you detect whether a STALL was sent? Does it matter whether there was data in the FIFO before STALL was set ... or when it was cleared?
No, I can't detect whether the stall was sent. I don't think whether there is data in the FIFO affects it (there is no mention of FIFOs being affected by stall in the manual).
The text you quoted implies it won't matter; clearing halts certainly _shouldn't_ affect fifos.
- Dave
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