Hello, i am testing my USB interface logic code modelled in vhdl for version 1.1. I need help on how to generate test data for testing the interface. i have tested the enumeration type of transfer by using a linux pc as usb host, but i find the data on the bus to be quite unreliable, i mean i have no control over what comes in as input? can anyone suggest any alternate source of data generation? thanks, Seetha
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