On Friday 20 January 2006 1:09 am, Mukund JB. wrote:
>
> Dear All,
>
> I am trying to settle some more clarification regarding the USB devices.
> Can someone please clarify the following?
>
> 1) OHCI & UHCI are the interfaces developed which with USB 1.1 devices.
> 2) EHCI is interfaces developed which with USB 2.0 devices. So, if it is
> USB 2.0 Host controller, may be then it is using the EHCI interface.
There are other interfaces for both full/low speed hosts ("USB 1.1" as
well as "USB 2.0") and for high speed ones (only "USB 2.0"). Those are
common primarily because of PCs. Where gate count matters, silicon
vendors may find it better to avoid "standard" register interfaces.
I've used high speed hosts that aren't EHCI, and full/low speed ones
that aren't OHCI or UHCI ...
> 3) OTG device is not separate from USB Host controller (HC) and instead
> it is an additional feature of the HC.
It's not just an HC feature ... both host and peripheral side support
is needed, and it adds role selection (and session activation) to both
of them. It's more accurate to say that the OTG support is coupled
with the USB transceiver/PHY that which host and peripheral drivers use.
> 4) I guess, I can simply make OTG work by adding a layer on top of the
> USB Host Controller Driver (STACK) & Device controller Driver.
I've seen no hardware that could work that way ... you can't design the
stack without reference to the hardware.
> OTG Layer
> -------------------
> DC Driver HC Driver(STACK)
> (Device controller)
>
> With this architecture, I guess the OTG would be capable of invoking any
> of these 2 Drivers dynamically.
Not how I'd put it at all, but some people draw layering pictures
upside down and maybe that's all that's going on there...
The OTG hardware (and its driver) kicks in before drivers for either
host or peripheral roles; so it's a lower level driver, not (as you
drew it) a higher level one.
You need to read both the OTG 1.0a and USB 2.0 specs, as well as the
specs for your host and peripheral controllers. To the extent that
your PHY is documented and accessible, you'll need to understand how
that interacts with the controllers too.
In the Linux kernel, see the isp1301_omap driver for one example of
how to fit things together.
- Dave
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