On Mon, 1 May 2006, Pete Zaitcev wrote:

> On Mon, 24 Apr 2006 11:55:51 -0400 (EDT), Alan Stern <[EMAIL PROTECTED]> 
> wrote:
> 
> > Before submitting the patch, it seemed like a good idea to check with you 
> > and make sure it doesn't cause any problems.  I'd appreciate it if you 
> > could try it out and let me know what happens.  The patch is based on 
> > 2.6.17-rc2.
> 
> Everything works fine here. I verified briefly that USBR do not get stuck
> and that performace is adquate.

Good; thanks for testing.

> The code looks fine though this concerns me a little:
> 
> > +                   __le32 old_status, new_status, hw_status;
> > +
> > +                   /* Do this carefully because the hardware might
> > +                    * be updating td->status right now.  There's still
> > +                    * a race because the controller might already have
> > +                    * fetched the old value and be almost ready to
> > +                    * overwrite the IOC with a new value.  Nothing
> > +                    * much we can do if that happens. */
> > +                   old_status = cpu_to_le32(status);
> > +                   new_status = cpu_to_le32(status | TD_CTRL_IOC);
> > +                   hw_status = cmpxchg(&qh->next_td->status,
> > +                                   old_status, new_status);
> > +                   if (hw_status != old_status)
> > +                           goto restart;
> > +           }

It concerned me also.  However it seemed important, and you left it out 
of your initial implementation.

> The cmpxchg() is a second class citizen in platform API, so it may not
> be implemented, or is implemented without any atomicity guarantees.
> I'm pretty sure some CPUs cannot make these guarantees when they contend
> with device DMA rather than other CPUs.
> 
> I don't know what to do about this. It's tempting to ignore the issue
> and say that owners of obscure platforms deserve what they get...

My hope was that people wouldn't use UHCI controllers on those troublesome 
platforms.  :-)  More seriously, it is true that UHCI is confined to a 
relatively small set of platforms.

Is there some way to discover at buildtime or runtime whether cmpxchg is
atomic with respect to DMA access?  (Should I post this question on LKML?)  
If it turns out not to be atomic, that code could simply be skipped.  It
would slow things down a little, since FSBR wouldn't get turned back on
right away, but that's not as bad as overwriting a completion status.  
Better suboptimal than wrong.

Alan Stern



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