On Thu, Oct 25, 2018 at 03:33:53PM -0700, aj...@nvidia.com wrote:
> Latest NVIDIA GPU cards have a Cypress CCGx Type-C controller
> over I2C interface.
>
> This UCSI I2C driver uses I2C bus driver interface for communicating
> with Type-C controller.
> + /*
> + * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
> + * register write will push response which must be cleared.
> + */
> + do {
> + status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
> + if (status < 0)
> + return status;
> +
> + if (!data)
> + return 0;
> +
> + status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
> + if (status < 0)
> + return status;
> +
> + usleep_range(10000, 11000);
> + } while (data && --count);
I don't see any point to check data here. How can it be different from the
check above?
> + return -ETIMEDOUT;
--
With Best Regards,
Andy Shevchenko
