On Wed, Jan 30, 2013 at 04:29:40PM +0100, Sascha Hauer wrote:
> From: Michael Grzeschik <m.grzesc...@pengutronix.de>
>
> +static void hw_phymode_configure(struct ci13xxx *ci)
> +{
> + u32 portsc;
> +
> + /*
> + * The lpm version has the corresponding bits in the devlc register.
> + * Currently not implemented.
> + */
> + if (ci->hw_bank.lpm)
> + return;
> +
> + switch (ci->platdata->phy_mode) {
> + case USBPHY_INTERFACE_MODE_UTMI:
> + portsc = PORTSC_PTS_PTW_UTMI;
> + break;
> + case USBPHY_INTERFACE_MODE_UTMIW:
> + portsc = PORTSC_PTS_PTW_UTMIW;
> + break;
> + case USBPHY_INTERFACE_MODE_ULPI:
> + portsc = PORTSC_PTS_PTW_ULPI;
> + break;
> + case USBPHY_INTERFACE_MODE_SERIAL:
> + portsc = PORTSC_PTS_PTW_SERIAL;
> + break;
> + case USBPHY_INTERFACE_MODE_HSIC:
> + portsc = PORTSC_PTS_PTW_HSIC;
> + break;
> + default:
> + return;
> + }
> +
> + hw_write(ci, OP_PORTSC, PORTSC_PTS_PTW, portsc);
> +
> + mdelay(10);
Please use usleep_range, can we recall which platform needs it?
As we as I know, there is no such delay at FSL internal release
code.
--
Best Regards,
Peter Chen
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