Hi, On Tue, Feb 26, 2013 at 07:23:02PM -0800, Paul Zimmerman wrote: > The core code provides basic services for accessing and managing > the DWC_otg hardware. These services are used by both the Host > Controller Driver and (in future) the Peripheral Controller Driver. > > Signed-off-by: Paul Zimmerman <pa...@synopsys.com> > ---
just a two comments below, besides them you can add:
Reviewed-by: Felipe Balbi <ba...@ti.com>
> + if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
> + !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
> + op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
> + op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
> + op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
> + dev_err(hsotg->dev,
> + "Hardware does not support descriptor DMA mode
> -\n"
> + "falling back to buffer DMA mode.\n");
one nit-pick here. You shouldn't break the line like that, instead you
should (also making error message a little shorter):
dev_err(hsotg->dev,
"No support for descriptor DMA mode\n");
dev_err(hsotg->dev,
"falling back to buffer DMA mode.\n");
> + dev_err(hsotg->dev,
> + "%s: Unable to clear enable on
> channel %d\n",
> + __func__, i);
__func__ isn't necessary here since this is the only message of its
kind.
--
balbi
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