>>>>> "Max" == Max Filippov <[email protected]> writes:
> According to CY7C67300 specification HPI read and write cycle duration
> Tcyc must be at least 6T long, where T is 1/48MHz, which is 125ns.
> Without this delay fast host processor cannot write to chip registers.
> Add proper ndelay to hpi_{read,write}_reg.
It would be good to add a sensible named define (with the above
description) as a comment and use that instead of the magic 125 constant
in the code.
With that fixed:
Acked-by: Peter Korsgaard <[email protected]>
--
Bye, Peter Korsgaard
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