On some boards powered by iMX6Q rev1.0 I get non-working USB Host 1
(connected to a hub, no other devices are connected to this hub) and
repeating resets from the chipidea host driver (with ported pm support
from Freescale):
....
[ 25.481714] usb 2-1: reset high-speed USB device number 2 using ci_hdrc
[ 27.491716] usb 2-1: reset high-speed USB device number 2 using ci_hdrc
[ 29.501721] usb 2-1: reset high-speed USB device number 2 using ci_hdrc
....
As for me it seems that usb phy test clock gating may be done
incorrectly, on disconnection it is running, and on connection it is
gated, but may be it is the intention, unfortunately iMX6Q RM is not
a satisfactory source of information on the topic.
Either complete disabling of loopback for the host or inverting test
clock gating solves my problem, this change proposes to invert test
clock gating setting.
Signed-off-by: Vladimir Zapolskiy <vladimir_zapols...@mentor.com>
Cc: Peter Chen <peter.c...@freescale.com>
---
drivers/usb/phy/phy-mxs-usb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index 0e0c415..fbd079f 100644
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -231,7 +231,7 @@ static void __mxs_phy_disconnect_line(struct mxs_phy
*mxs_phy, bool disconnect)
if (disconnect)
writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
- base + HW_USBPHY_DEBUG_CLR);
+ base + HW_USBPHY_DEBUG_SET);
if (mxs_phy->port_id == 0) {
reg = disconnect ? ANADIG_USB1_LOOPBACK_SET
@@ -249,7 +249,7 @@ static void __mxs_phy_disconnect_line(struct mxs_phy
*mxs_phy, bool disconnect)
if (!disconnect)
writel_relaxed(BM_USBPHY_DEBUG_CLKGATE,
- base + HW_USBPHY_DEBUG_SET);
+ base + HW_USBPHY_DEBUG_CLR);
/* Delay some time, and let Linestate be SE0 for controller */
if (disconnect)
--
1.7.10.4
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