Hi, On Fri, Nov 14, 2014 at 08:03:15AM +0800, Peter Chen wrote: > Add controller reset API, it may be used for host/otg driver in future.
you need a better commit log here. How would it be used ? when ? And,
more importantly, why ?
Why would we need to reset the IP outside of ->probe() ?
I don't oppose to the refactoring, but why would we ever need to reset
this IP ?
> Signed-off-by: Peter Chen <peter.c...@freescale.com>
> ---
>
> Changes for v2:
> - Add return value check for controller reset at hw_device_reset
>
> drivers/usb/chipidea/core.c | 30 +++++++++++++++++++++++++++---
> 1 file changed, 27 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
> index bd74f27..dffd89b 100644
> --- a/drivers/usb/chipidea/core.c
> +++ b/drivers/usb/chipidea/core.c
> @@ -385,6 +385,26 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
> }
>
> /**
> + * hw_controller_reset: do controller reset
> + * @ci: the controller
> + *
minor nit: indentation
> + * This function returns an error code
> + */
> +static int hw_controller_reset(struct ci_hdrc *ci)
> +{
> + int count = 0;
> +
> + hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
> + while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
> + udelay(10);
> + if (count++ > 1000)
> + return -ETIMEDOUT;
> + }
> +
> + return 0;
> +}
> +
> +/**
> * hw_device_reset: resets chip (execute without interruption)
> * @ci: the controller
> *
> @@ -392,13 +412,17 @@ static int ci_usb_phy_init(struct ci_hdrc *ci)
> */
> int hw_device_reset(struct ci_hdrc *ci, u32 mode)
> {
> + int ret;
> +
> /* should flush & stop before reset */
> hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
> hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
>
> - hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
> - while (hw_read(ci, OP_USBCMD, USBCMD_RST))
> - udelay(10); /* not RTOS friendly */
> + ret = hw_controller_reset(ci);
> + if (ret) {
> + dev_err(ci->dev, "error for reset, ret=%d\n", ret);
> + return ret;
> + }
>
> if (ci->platdata->notify_event)
> ci->platdata->notify_event(ci,
> --
> 1.9.1
>
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