Hi, On Sat, Jan 31, 2015 at 01:18:46PM +0200, Antti Seppälä wrote: > This patch switches calls to readl/writel to their > dwc2_readl/dwc2_writel equivalents which preserve platform endianness. > > This patch is necessary to access dwc2 registers correctly on big endian > systems such as the mips based SoCs made by Lantiq. Then dwc2 can be
I don't get it, why is it so that only mips needs this ? What's special
about mips' writel/readl implementation that it can't be used here ?
This works for everybody else.
Is it so that dwc2 and cpu endianness don't match here ?
> used to replace ifx-hcd driver for Lantiq platforms found e.g. in
> OpenWrt.
>
> The patch was autogenerated with the following commands:
> $EDITOR core.h
> sed -i "s/\<readl\>/dwc2_readl/g" *.c hcd.h hw.h
> sed -i "s/\<writel\>/dwc2_writel/g" *.c hcd.h hw.h
weren't readl() and writel() already supposed to handle endianness for
us?
> Some files were then hand-edited to fix checkpatch.pl warnings about
> too long lines.
>
> Signed-off-by: Antti Seppälä <a.sepp...@gmail.com>
> Signed-off-by: Vincent Pelletier <plr.vinc...@gmail.com>
> ---
> diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
> index 7a70a13..d2a9d15 100644
> --- a/drivers/usb/dwc2/core.h
> +++ b/drivers/usb/dwc2/core.h
> @@ -44,16 +44,28 @@
> #include <linux/usb/phy.h>
> #include "hw.h"
>
> -#ifdef DWC2_LOG_WRITES
> -static inline void do_write(u32 value, void *addr)
> +static inline u32 dwc2_readl(const void __iomem *addr)
> {
> - writel(value, addr);
> - pr_info("INFO:: wrote %08x to %p\n", value, addr);
> + u32 value = __raw_readl(addr);
> +
> + /* In order to preserve endianness __raw_* operation is used. Therefore
> + a barrier is needed to ensure IO access is not re-ordered across
> + reads or writes */
wrong comment style.
--
balbi
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