On Sat, Sep 03, 2016 at 12:16:29AM +0200, Peter Zijlstra wrote: > On Sat, Sep 03, 2016 at 12:14:13AM +0200, Peter Zijlstra wrote: > > On Fri, Sep 02, 2016 at 04:16:54PM -0400, Alan Stern wrote: > > > > > > Actually, that's not entirely true (although presumably it works okay > > > for most architectures). > > > > Yeah, all load-store archs (with exception of PowerPC and ARM64 and > > possibly MIPS) implement ACQUIRE with a general fence (after the ll/sc). > > > > ( and MIPS doesn't use their fancy barriers in Linux ) > > > > PowerPC does the full fence for smp_mb__before_spinlock, which leaves > > ARM64, I'm not sure its correct, but I'm way too tired to think about > > that now. > > > > The TSO archs imply full barriers with all atomic RmW ops and are > > therefore also good. > > > > Forgot to Cc Will. Will, does ARM64 need to make smp_mb__before_spinlock > smp_mb() too?
Yes, probably. Just to confirm, the test is something like: CPU0 ---- Wx=1 smp_mb__before_spinlock() LOCK(y) Rz=0 CPU1 ---- Wz=1 smp_mb() Rx=0 and that should be forbidden? Will -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
