From: Mason
> Sent: 10 March 2017 15:06
...
> My RC drops packets not targeting its BAR0.
I suspect the fpga/cpld logic supports RC and endpoint modes
and is using much the same names for the registers (and logic
implementation).
If your cpu support more than 1GB of memory but only part is
PCIe accessible you'll have to ensure that all the memory
definitions are set correctly and 'bounce buffers' used for
some operations.
David
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