From: Robin Murphy
> Sent: 10 October 2017 16:25
...
> > That could 'just' be the hardware doing a 'readahead' of the ring.
> > Somewhat annoying if it is doing that across page boundaries.
>
> > Although, in that case, the read values wouldn't be used because the
> > last TRB is a link.
> > So that shouldn't stop the USB transfer - just gives an annoying error
> > message.
> > OTOH if the PCIe read completion ends up with an error status it might halt
> > the ring (or similar).
>
> Indeed, on my machine once the PCIe root complex gets an abort back from the
> IOMMU, the VL805 is basically dead until a hard reset. The grotty diff
> below does resolve that particular issue, but I'm not sure I like it :/
Is it enough to only allocate 255 TRB per page instead of adding a
guard page?
David
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