Hi Gabor, [auto build test ERROR on wireless-drivers-next/master] [also build test ERROR on next-20170113] [cannot apply to v4.10-rc3] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniel-Golle/rt2x00-patches-form-OpenWrt-org/20170115-102250 base: https://git.kernel.org/pub/scm/linux/kernel/git/kvalo/wireless-drivers-next.git master config: x86_64-allyesdebian (attached as .config) compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 Note: the linux-review/Daniel-Golle/rt2x00-patches-form-OpenWrt-org/20170115-102250 HEAD 849367246e2b54e086e272ee2bd32b9983bc30fb builds fine. It only hurts bisectibility. All errors (new ones prefixed by >>): drivers/net/wireless/ralink/rt2x00/rt2800lib.c: In function 'rt2800_config_channel_rf3853': drivers/net/wireless/ralink/rt2x00/rt2800lib.c:2734:2: error: implicit declaration of function 'rt2800_adjust_freq_offset' [-Werror=implicit-function-declaration] rt2800_adjust_freq_offset(rt2x00dev); ^~~~~~~~~~~~~~~~~~~~~~~~~ drivers/net/wireless/ralink/rt2x00/rt2800lib.c: In function 'rt2800_init_registers': >> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:5027:36: error: >> 'TX_TXBF_CFG_0' undeclared (first use in this function) rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, 0x8000fc21); ^~~~~~~~~~~~~ drivers/net/wireless/ralink/rt2x00/rt2800lib.c:5027:36: note: each undeclared identifier is reported only once for each function it appears in >> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:5028:36: error: >> 'TX_TXBF_CFG_3' undeclared (first use in this function) rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, 0x00009c40); ^~~~~~~~~~~~~ >> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:5224:36: error: >> 'TX_FBK_CFG_3S_0' undeclared (first use in this function) rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, 0x12111008); ^~~~~~~~~~~~~~~ >> drivers/net/wireless/ralink/rt2x00/rt2800lib.c:5225:36: error: >> 'TX_FBK_CFG_3S_1' undeclared (first use in this function) rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, 0x16151413); ^~~~~~~~~~~~~~~ cc1: some warnings being treated as errors vim +/TX_TXBF_CFG_0 +5027 drivers/net/wireless/ralink/rt2x00/rt2800lib.c 5021 0x00000000); 5022 } 5023 } else if (rt2x00_rt(rt2x00dev, RT3883)) { 5024 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402); 5025 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5026 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00040000); > 5027 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_0, > 0x8000fc21); > 5028 rt2800_register_write(rt2x00dev, TX_TXBF_CFG_3, > 0x00009c40); 5029 } else if (rt2x00_rt(rt2x00dev, RT5390) || 5030 rt2x00_rt(rt2x00dev, RT5392)) { 5031 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5032 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5033 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5034 } else if (rt2x00_rt(rt2x00dev, RT5592)) { 5035 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); 5036 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 5037 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 5038 } else { 5039 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 5040 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 5041 } 5042 5043 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®); 5044 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32); 5045 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0); 5046 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0); 5047 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0); 5048 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0); 5049 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1); 5050 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0); 5051 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0); 5052 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg); 5053 5054 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®); 5055 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 5056 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32); 5057 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 5058 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 5059 5060 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®); 5061 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 5062 if (rt2x00_rt(rt2x00dev, RT3883)) { 5063 drv_data->max_psdu = 3; 5064 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 3); 5065 } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) || 5066 rt2x00_rt(rt2x00dev, RT2883) || 5067 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) { 5068 drv_data->max_psdu = 2; 5069 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2); 5070 } else { 5071 drv_data->max_psdu = 1; 5072 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1); 5073 } 5074 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 10); 5075 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 10); 5076 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 5077 5078 rt2800_register_read(rt2x00dev, LED_CFG, ®); 5079 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70); 5080 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30); 5081 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3); 5082 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3); 5083 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3); 5084 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3); 5085 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1); 5086 rt2800_register_write(rt2x00dev, LED_CFG, reg); 5087 5088 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 5089 5090 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®); 5091 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15); 5092 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31); 5093 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000); 5094 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0); 5095 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0); 5096 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1); 5097 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 5098 5099 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®); 5100 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1); 5101 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1); 5102 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 1); 5103 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0); 5104 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 0); 5105 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 5106 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 5107 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 5108 5109 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®); 5110 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3); 5111 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0); 5112 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1); 5113 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5114 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5115 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5116 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5117 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5118 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5119 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1); 5120 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 5121 5122 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®); 5123 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3); 5124 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0); 5125 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1); 5126 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 5127 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5128 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5129 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5130 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5131 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5132 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1); 5133 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 5134 5135 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®); 5136 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004); 5137 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 1); 5138 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5139 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5140 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5141 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5142 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5143 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5144 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5145 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0); 5146 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 5147 5148 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®); 5149 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 5150 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 1); 5151 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5152 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5153 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5154 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5155 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5156 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5157 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5158 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0); 5159 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 5160 5161 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®); 5162 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004); 5163 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 1); 5164 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1); 5165 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5166 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5167 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5168 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 5169 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5170 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 5171 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0); 5172 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 5173 5174 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®); 5175 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084); 5176 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 1); 5177 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1); 5178 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0); 5179 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 5180 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1); 5181 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 5182 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 5183 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 5184 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0); 5185 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 5186 5187 if (rt2x00_is_usb(rt2x00dev)) { 5188 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006); 5189 5190 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®); 5191 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0); 5192 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0); 5193 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0); 5194 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0); 5195 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3); 5196 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0); 5197 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0); 5198 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0); 5199 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0); 5200 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg); 5201 } 5202 5203 /* 5204 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1 5205 * although it is reserved. 5206 */ 5207 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®); 5208 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1); 5209 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1); 5210 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1); 5211 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1); 5212 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1); 5213 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1); 5214 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0); 5215 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0); 5216 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88); 5217 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0); 5218 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg); 5219 5220 reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002; 5221 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg); 5222 5223 if (rt2x00_rt(rt2x00dev, RT3883)) { > 5224 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_0, > 0x12111008); > 5225 rt2800_register_write(rt2x00dev, TX_FBK_CFG_3S_1, > 0x16151413); 5226 } 5227 5228 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®); --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
